A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider.

Baoyong Chi Xueyi Yu Woogeun Rhee Zhihua Wang

Published in: ISCAS (2007)

Keyphrases

power consumption
high speed
filter bank
digital media
low pass filter
digital filters
phase locked loop
website
computationally efficient
generation process
high pass
frequency distribution
duty cycle
iir filters