Xin-Yu Shih

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 24

Top Topics

Reconfigurable Hardware

Support Vector Machine

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Xin-Yu Shih, Yu-Chen Lee, Geng-Hong Li, Jia-Han Xie
High-Area-Efficiency Polar Decoder Chip Architecture Reconfiguring SCL-Decoding With Reconfigurable Pipelined Sorter and SCF-Decoding With Non-Uniform 4-Segment CRC. IEEE Trans. Circuits Syst. II Express Briefs 71 (4) (2024)
Xin-Yu Shih, Yao Chiu, Hsiang-En Wu
Design and Implementation of Decision-Tree (DT) Online Training Hardware Using Divider-Free GI Calculation and Speeding-Up Double-Root Classifier. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (2) (2023)
Xin-Yu Shih, Hsiang-En Wu, Ming-Xian Cai
Design and Implementation of Dual-Mode Support Vector Machine (SVM) Trainer and Classifier Chip Architecture for Human Disease Detection Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (12) (2023)
Xin-Yu Shih, Chen-Yen Song, Yao-Yu Lu
Unified chip hardware architecture of KD-tree mean-based trainer and speeding-up classifier with repeat-point searching for various applications. Integr. 93 (2023)
Xin-Yu Shih, Lok Hin Samuel Leung, Geng-Hong Li
Low-Cost Hardware Design of Fast 3D-Sorter Engine for Successive Cancellation List Polar-Decoders in 5G Applications. ICCE-Taiwan (2023)
Xin-Yu Shih, Hsiang-En Wu
Design Methodology of Queue-Based Fast Classification for Sequential Minimal Optimization in SVM ML-Training. ICCE-TW (2022)
Xin-Yu Shih, Hsiang-En Wu
Design and Analysis of 7x7 Median Filter with 8-Step Low-Complexity Fast Searching Approach for Undersea Image Processing Applications. ICCE-TW (2022)
Xin-Yu Shih, Ming-Jyun Wu, Hsiang-En Wu
A Systematic and Generic Correlation-Based Design Approach for Data Sample Reduction in ML-Training. ICCE-TW (2022)
Xin-Yu Shih, Jui-Hung Tsai, Bing-Xuan Li, Chi-Ping Huang
Reconfigurable Hardware Architecture of Area-Efficient Multimode Successive Cancellation (SC) Decoder. IEEE Trans. Circuits Syst. II Express Briefs 69 (4) (2022)
Xin-Yu Shih, Chen-Yen Song
Scalable and Reconfigurable Architecture of Modified KD-Tree ML-Classifier with 5-Point Searching. ICCE-TW (2022)
Xin-Yu Shih, Hong-Ru Chou
Flexible design and implementation of QC-Based LDPC decoder architecture for on-line user-defined matrix downloading and efficient decoding. Integr. 64 (2019)
Xin-Yu Shih
Design and Analysis of Cost-Efficient Ultra-High-Order Matched Filter Architecture Using 4-Phase Calculating Paths for Underwater Applications. ICCE-TW (2019)
Xin-Yu Shih
VLSI Architecture of 36-Mode Reconfigurable FFT Hardware Chip with Newly-Developed 2D-FIFO Arrangement Structure. ICSAI (2019)
Xin-Yu Shih, Hong-Ru Chou
Reconfigurable VLSI design of a changeable hybrid-radix FFT hardware architecture with 2D-FIFO storing structure for 3GPP LTE systems. ICT Express 4 (3) (2018)
Xin-Yu Shih, Po-Chun Huang, Hong-Ru Chou
VLSI design and implementation of a reconfigurable hardware-friendly Polar encoder architecture for emerging high-speed 5G system. Integr. 62 (2018)
Xin-Yu Shih, Hong-Ru Chou, Yue-Qu Liu
Design and Implementation of Flexible and Reconfigurable SDF-Based FFT Chip Architecture With Changeable-Radix Processing Elements. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2018)
Xin-Yu Shih, Hong-Ru Chou, Yue-Qu Liu
VLSI Design and Implementation of Reconfigurable 46-Mode Combined-Radix-Based FFT Hardware Architecture for 3GPP-LTE Applications. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2018)
Xin-Yu Shih, Hong-Ru Chou
A 2-D grouping FIFO based hardware architecture for supporting 36-mode hybrid-radix FFT design in 3GPP-LTE systems. GCCE (2017)
Xin-Yu Shih, Yue-Qu Liu, Hong-Ru Chou
Design Approaches. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2017)
Xin-Yu Shih, Hong-Ru Chou
Reconfigurable hardware design of low-area-cost computing kernel engine for different radixes of single-path delay feedback FFT systems. ICCE (2017)
Xin-Yu Shih, Yue-Qu Liu
Cost-efficient hardware design of coarse and fine rotation based FFT twiddle factor generator for 3GPP LTE applications. GCCE (2017)
Xin-Yu Shih, Po-Chun Huang, Yu-Chun Chen
LEGO-based VLSI design and implementation of polar codes encoder architecture with radix-2 processing engines. APCCAS (2016)
Xin-Yu Shih, Hong-Ru Chou, Yue-Qu Liu
Reconfigurable VLSI design of processing kernel for multiple-radix single-path delay feedback FFT systems. GCCE (2016)
Xin-Yu Shih, Po-Chun Huang, Yu-Chun Chen
High-speed low-area-cost VLSI design of polar codes encoder architecture using radix-k processing engines. GCCE (2016)
Hua Wang, Chun-Hsien Peng, Yaopei Chang, Richard Z. Huang, Chih-Wei Chang, Xin-Yu Shih, Chia-Jui Hsu, Paul C. P. Liang, Ali M. Niknejad, George Chien, Chao Long Tsai, H. C. Hwang
A Highly-Efficient Multi-Band Multi-Mode All-Digital Quadrature Transmitter. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2014)
Jie-Wei Lai, Chi-Hsueh Wang, Kaipon Kao, Anson Lin, Yi-Hsien Cho, Lan-chou Cho, Meng-Hsiung Hung, Xin-Yu Shih, Che-Min Lin, Sheng-Hong Yan, Yuan-Hung Chung, Paul C. P. Liang, Guang-Kaai Dehng, Hung-Sung Li, George Chien, Robert Bogdan Staszewski
13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS. ISSCC (2013)
Min-An Chao, Xin-Yu Shih, An-Yeu Wu
Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders. J. Signal Process. Syst. 68 (2) (2012)
Yu-Hsin Chen, Yi-Ju Chen, Xin-Yu Shih, An-Yeu Wu
A Channel-Adaptive Early Termination strategy for LDPC decoders. SiPS (2009)
Min-An Chao, Jen-Yang Wen, Xin-Yu Shih, An-Yeu Wu
A Triple-mode LDPC Decoder Design for IEEE 802.11n SYSTEM. ISCAS (2009)
Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu Wu
19-mode LDPC decoder chip for mobile WiMAX applications. ASP-DAC (2009)
Cheng-Zhou Zhan, Xin-Yu Shih, An-Yeu Wu
High-performance scheduling algorithm for partially parallel LDPC decoder. ICASSP (2008)
Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu Wu
52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 µm CMOS Process. IEEE J. Solid State Circuits 43 (3) (2008)