Hong-Ru Chou

Publication Activity (10 Years)

Years Active: 2016-2019
Publications (10 Years): 9

Top Topics

Hardware Architecture

Fourier Transform

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Xin-Yu Shih, Hong-Ru Chou
Flexible design and implementation of QC-Based LDPC decoder architecture for on-line user-defined matrix downloading and efficient decoding. Integr. 64 (2019)
Xin-Yu Shih, Hong-Ru Chou
Reconfigurable VLSI design of a changeable hybrid-radix FFT hardware architecture with 2D-FIFO storing structure for 3GPP LTE systems. ICT Express 4 (3) (2018)
Xin-Yu Shih, Po-Chun Huang, Hong-Ru Chou
VLSI design and implementation of a reconfigurable hardware-friendly Polar encoder architecture for emerging high-speed 5G system. Integr. 62 (2018)
Xin-Yu Shih, Hong-Ru Chou, Yue-Qu Liu
Design and Implementation of Flexible and Reconfigurable SDF-Based FFT Chip Architecture With Changeable-Radix Processing Elements. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2018)
Xin-Yu Shih, Hong-Ru Chou, Yue-Qu Liu
VLSI Design and Implementation of Reconfigurable 46-Mode Combined-Radix-Based FFT Hardware Architecture for 3GPP-LTE Applications. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2018)
Xin-Yu Shih, Hong-Ru Chou
A 2-D grouping FIFO based hardware architecture for supporting 36-mode hybrid-radix FFT design in 3GPP-LTE systems. GCCE (2017)
Xin-Yu Shih, Yue-Qu Liu, Hong-Ru Chou
Design Approaches. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2017)
Xin-Yu Shih, Hong-Ru Chou
Reconfigurable hardware design of low-area-cost computing kernel engine for different radixes of single-path delay feedback FFT systems. ICCE (2017)
Xin-Yu Shih, Hong-Ru Chou, Yue-Qu Liu
Reconfigurable VLSI design of processing kernel for multiple-radix single-path delay feedback FFT systems. GCCE (2016)