High-Area-Efficiency Polar Decoder Chip Architecture Reconfiguring SCL-Decoding With Reconfigurable Pipelined Sorter and SCF-Decoding With Non-Uniform 4-Segment CRC.
Xin-Yu ShihYu-Chen LeeGeng-Hong LiJia-Han XiePublished in: IEEE Trans. Circuits Syst. II Express Briefs (2024)
Keyphrases
- decoding algorithm
- decoding process
- video decoder
- low power consumption
- low cost
- joint source channel
- ldpc codes
- video codec
- error control
- multiview video coding
- soft decision
- high speed
- reed solomon
- data flow
- hardware implementation
- low density parity check
- pixel domain
- vlsi implementation
- rate allocation
- image transmission
- reconfigurable hardware
- noisy channel
- coding scheme
- signal processing