Tomokazu Ishihara

Publication Activity (10 Years)

Years Active: 2006-2008
Publications (10 Years): 0

Publications

Kosuke Mizuno, Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto
An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encoding. ICECS (2008)
Yuichiro Murachi, Kosuke Mizuno, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto
A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding. ISCAS (2008)
Yuichiro Murachi, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto
A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer. IEICE Trans. Electron. (4) (2008)
Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Tetsuro Matsuno
A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing. VLSI-SoC (2006)
Junichi Miyakoshi, Yuichiro Murachi, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto
A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing. IEICE Trans. Electron. (11) (2006)
Junichi Miyakoshi, Yuichiro Murachi, Tetsuro Matsuno, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masayuki Miyama, Masahiko Yoshimoto
A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2006)