A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer.
Yuichiro MurachiJunichi MiyakoshiMasaki HamamotoTakahiro IinumaTomokazu IshiharaFang YinJangchung LeeHiroshi KawaguchiMasahiko YoshimotoPublished in: IEICE Trans. Electron. (2008)
Keyphrases
- motion estimation
- systolic array
- reconfigurable architecture
- search range
- motion compensation
- motion vectors
- motion compensated
- data flow
- video coding
- parallel architecture
- block matching
- video sequences
- image sequences
- computer vision
- optical flow
- processor core
- power consumption
- low cost
- video compression
- inter frame
- motion model
- computational complexity
- rate distortion
- image segmentation
- motion field
- stereo matching
- level set
- graphical models
- information systems