A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture.
Junichi MiyakoshiYuichiro MurachiTetsuro MatsunoMasaki HamamotoTakahiro IinumaTomokazu IshiharaHiroshi KawaguchiMasayuki MiyamaMasahiko YoshimotoPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2006)
Keyphrases
- systolic array
- processor array
- motion estimation
- parallel architecture
- data flow
- reconfigurable architecture
- block matching
- parallel processing
- processor core
- parallel algorithm
- motion vectors
- image sequences
- shared memory
- mesh connected
- power consumption
- optical flow
- parallel implementation
- ibm zenterprise
- massively parallel
- real time
- management system
- signal processing
- computational complexity
- block size
- video sequences
- data management