A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding.
Yuichiro MurachiKosuke MizunoJunichi MiyakoshiMasaki HamamotoTakahiro IinumaTomokazu IshiharaFang YinJangchung LeeTetsuya KaminoHiroshi KawaguchiMasahiko YoshimotoPublished in: ISCAS (2008)
Keyphrases
- motion estimation
- video encoder
- mode selection
- video coding
- low complexity
- video encoding
- single chip
- motion vectors
- high speed
- video compression
- inter frame
- macroblock
- motion compensation
- mode decision
- rate distortion
- coding efficiency
- variable block size
- gate array
- intra coding
- motion compensated
- video compression standard
- power consumption
- block matching
- video coding standard
- video sequences
- chip design
- image sequences
- inter layer
- optical flow
- video coder
- video codec
- wyner ziv video coding
- computational complexity
- motion field
- low power
- super resolution
- intra frame
- search range
- reference frame
- motion model
- compression efficiency
- motion estimation algorithm
- prediction mode
- compressed domain
- power dissipation
- rate control
- distributed video coding
- motion estimator
- computer vision
- block size
- signal processing
- bit rate
- decoding process
- video quality
- intra prediction
- bitstream
- quantization parameter
- error concealment
- high coding efficiency
- scalable video coding
- compressed video
- inter mode decision