Takuji Ogihara

Publication Activity (10 Years)

Years Active: 1981-1993
Publications (10 Years): 0

Publications

Yasushi Koseko, Takuji Ogihara, Shinichi Murai
Tri-state bus conflict checking method for ATPG using BDD. ICCAD (1993)
Takuji Ogihara, Yasushi Koseko, Genichi Yonemori, Hiroyuki Kawai
Testable design and support tool for cell based test. ITC (1990)
Yasushi Koseko, C. Hiramine, Takuji Ogihara, Shinichi Murai
Rule-based testability rule check program. ICCD (1990)
Takuji Ogihara, K. Muroi, Genichi Yonemori, Shinichi Murai
MULTES/IS: An Effective and Reliable Test Generation System for Partial Scan and Non-Scan Synchronous Circuits. DAC (1989)
Takuji Ogihara, Shuichi Saruyama, Shinichi Murai
Test generation for sequential circuits using individual initial value propagation. ICCAD (1988)
Takuji Ogihara, H. Toyoshima, Shinichi Murai
ASTA: LSI Design Management System. DAC (1987)
Takuji Ogihara, Shuichi Saruyama, Shinichi Murai
PATEGE: an automatic DC parametric test generation system for series gated ECL circuits. DAC (1985)
Kiyoshi Enomoto, Shunichiro Nakamura, Takuji Ogihara, Shinichi Murai
LORES-2: A Logic Reorganization System. IEEE Des. Test 2 (5) (1985)
Takuji Ogihara, Shinichi Murai, Yuzo Takamatsu, Kozo Kinoshita, Hideo Fujiwara
Test generation for scan design circuits with tri-state modules and bidirectional terminals. DAC (1983)
Chiyoji Tanaka, Shinichi Murai, Shunichiro Nakamura, Takuji Ogihara, Masayuki Terai, Kozo Kinoshita
An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2. DAC (1981)