Stephen A. Szygenda

Publication Activity (10 Years)

Years Active: 1970-2014
Publications (10 Years): 0

Top Topics

Knowledge Compilation

Multi Dimensional

Probability Distribution

Top Venues

Publications

Mitchell A. Thornton, Theodore W. Manikas, Stephen A. Szygenda, Shinobu Nagayama
System Probability Distribution Modeling Using MDDs. ISMVL (2014)
Gerard Ibarra, Jerrell T. Stracener, Stephen A. Szygenda
A Systems Engineering Approach for Identifying the Most Critical Links of a Highway System: A Framework Consisting of a Methodology and Mathematical Model. IEEE Syst. J. 2 (2) (2008)
Chad M. Lawler, Michael A. Harper, Stephen A. Szygenda, Mitchell A. Thornton
Components of disaster-tolerant computing: analysis of disaster recovery, IT application downtime and executive visibility. Int. J. Bus. Inf. Syst. 3 (3) (2008)
Ralph Marczynski, Mitchell A. Thornton, Stephen A. Szygenda
Test vector generation and classification using FSM traversals. ISCAS (5) (2004)
Lun Li, Mitchell A. Thornton, Stephen A. Szygenda
A Genetic Approach for Conjunction Scheduling in Symbolic Equivalence Checking. ISVLSI (2004)
Sungho Kang, Stephen A. Szygenda
Accurate Logic Simulation by Overcoming the Unknown Value Propagation Problem. Simul. 79 (2) (2003)
Charles Wiley, A. T. Campbell III, Stephen A. Szygenda, Donald S. Fussell, Fred Hudson
Multiresolution BSP Trees Applied to Terrain, Transparency, and General Objects. Graphics Interface (1997)
Saghir A. Shaikh, Stephen A. Szygenda
Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation. Annual Simulation Symposium (1997)
Youngmin Hur, Saghir A. Shaikh, Silvian Goldenberg, D. Kacprzak, Stephen A. Szygenda
Concurrent Fault and Design Error Simulation in Interactive Simulation Automation System. Annual Simulation Symposium (1997)
Youngmin Hur, Stephen A. Szygenda
A Simulation Tool for Design Error Models Utilizing Error Compression and Sampling. Annual Simulation Symposium (1996)
Youngmin Hur, Stephen A. Szygenda
A Graphical Simulation and Automatic Model Generation System. ESM (1996)
Saghir A. Shaikh, Silvian Goldenberg, Stephen A. Szygenda
FERS: A Concurrent Concurrent Fault and Design Error Simulator. PDPTA (1996)
Sungho Kang, Youngmin Hur, Stephen A. Szygenda
A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture. VLSI Design 4 (2) (1996)
E. Scott Fehr, Stephen A. Szygenda, Granville E. Ott
An Integrated Hardware Array for Very High Speed Logic Simulation. VLSI Design 4 (2) (1996)
Brian Grayson, Saghir A. Shaikh, Stephen A. Szygenda
Statistics on concurrent fault and design error simulation. ICCD (1995)
Youngmin Hur, Stephen A. Szygenda
Special purpose array processor for digital logic simulation. Annual Simulation Symposium (1995)
Youngmin Hur, Stephen A. Szygenda, E. Scott Fehr, Granville E. Ott, Sungho Kang
Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation. HPCA (1995)
Sungho Kang, Stephen A. Szygenda
Design Validation: Comparing Theoretical and Empirical Results of Design Error Modeling. IEEE Des. Test Comput. 11 (1) (1994)
Sungho Kang, Stephen A. Szygenda
Automatic Simulator Generation System. Simul. 63 (6) (1994)
Shuchih Ernest Chang, Stephen A. Szygenda
Automatic Functional Model Generation for Parallel Fault and Design Error Simulations. Int. J. Artif. Intell. Tools 3 (2) (1994)
Sungho Kang, Stephen A. Szygenda
The simulation automation system (SAS); concepts, implementation, and results. IEEE Trans. Very Large Scale Integr. Syst. 2 (1) (1994)
Charles Wiley, K. M. Lau, Stephen A. Szygenda
m3D: A Multidimensional Dynamic Configurable Router. ISCAS (1993)
Sungho Kang, Stephen A. Szygenda
Automatic VHDL Model Generation System. CHDL (1993)
Sungho Kang, Stephen A. Szygenda
New design error modeling and metrics for design validation. EURO-DAC (1992)
Cheng-I Chuang, Stephen A. Szygenda, James D. Baker
The automatic element routine generator: an automatic programming tool for functional simulator design. Annual Simulation Symposium (1992)
Sungho Kang, Stephen A. Szygenda
Modeling and Simulation of Design Errors. ICCD (1992)
Jin-Hyeung Kong, Stephen A. Szygenda
MixMOS: a mixed-level simulator for digital MOS circuits using a new algebraic approach. Comput. Aided Des. 22 (10) (1990)
Asad Karim, Stephen A. Szygenda
SMARTGEN: The Implementation of an Expert System for the Generation of Digital Logic Diagnostic Tests. IEA/AIE (Vol. 1) (1988)
Stephen A. Szygenda, M. Wilson
Technology transfer: commercializing university research. FJCC (1987)
Ajoy K. Bose, Stephen A. Szygenda
Detection of static and dynamic hazards in logic nets. DAC (1977)
Ajoy K. Bose, Stephen A. Szygenda
Design of a diagnosable and fault-tolerant input/output controller. AFIPS National Computer Conference (1977)
N. Billawala, Stephen A. Szygenda, Ewald W. Thomson
A Data Structure and Drive Mechanism for a Table-Driven Simulation System Employing Multilevel Structural Representations of Digital Systems. ICSE (1976)
Stephen A. Szygenda, Edward W. Thompson
Modeling and Digital Simulation for Design Verification and Diagnosis. IEEE Trans. Computers 25 (12) (1976)
Stephen A. Szygenda
Digital Systems Simulation. Computer 8 (3) (1975)
Edward W. Thompson, Stephen A. Szygenda
Digital Logic Simulation in a Time-Based, Table-Driven Environment. Computer 8 (3) (1975)
Stephen A. Szygenda, Edward W. Thompson
Digital Logic Simulation in a Time-Based, Table-Driven Environment. Computer 8 (3) (1975)
Edward W. Thompson, Stephen A. Szygenda
Three levels of accuracy for the simulation of different fault types in digital systems. DAC (1975)
Edward W. Thompson, Stephen A. Szygenda, N. Billawala, R. Pierce
Timing analysis for digital fault simulation using assignable delays. DAC (1974)
Stephen A. Szygenda, Anthony A. Lekkos, John L. Fike
Implemented techniques for handling spikes in an assignable delay simulator. WSC (1974)
Stephen A. Szygenda, Anthony A. Lekkos
Integrated techniques for functional and gate-level digital logic simulation. DAC (1973)
John M. Hemphill, Stephen A. Szygenda
Deriving Design Guidelines for Diagnosable Computer Systems. ISCA (1973)
John L. Fike, Stephen A. Szygenda
Techniques and modules for element specification in a time - delay logic simulator. ANSS (1973)
Stephen A. Szygenda
TEGAS2 - anatomy of a general purpose TEST GENERATION AND SIMULATION system for digital logic. DAC (1972)
Stephen A. Szygenda, Edward W. Thompson
Fault insertion techniques and models for digital logic simulation. AFIPS Fall Joint Computing Conference (2) (1972)
Cliff W. Hemming Jr., Stephen A. Szygenda
Modular requirements for digital logic simulation at a predefined functional level. ACM Annual Conference (1) (1972)
Stephen A. Szygenda, Michael J. Flynn
Coding techniques for failure recovery in a distributive modular memory organization. AFIPS Spring Joint Computing Conference (1971)
Stephen A. Szygenda, Cliff W. Hemming Jr., John M. Hemphill
Time flow mechanisms for use in digital logic simulation. WSC (1971)
Stephen A. Szygenda, David M. Rouse, Edward W. Thompson
A model and implementation of a universal time delay simulator for large digital nets. AFIPS Spring Joint Computing Conference (1970)