Shaolan Li

Publication Activity (10 Years)

Years Active: 2016-2024
Publications (10 Years): 43

Top Topics

Fully Automated

Analog Circuits

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Tian Xie, Ken Li, Tzu-Han Wang, Wei-En Lee, Engin Esen, Dong Suk Kang, Shaolan Li
An 82dB-SNDR Input-Driving-Relaxed Noise-Shaping SAR with Amplifier-Reused In-Loop Buffering and NTF Leakage Reshaping. CICC (2024)
Yan Lu, Shaolan Li
Guest Editorial 2023 Custom Integrated Circuits Conference. IEEE J. Solid State Circuits 59 (3) (2024)
Xitie Zhang, Evren F. Arkan, Coskun Tekes, Tzuhan Wang, F. Levent Degertekin, Shaolan Li
Guidewire IVUS SoC with ±50°-Range Plane Wave Transmit Beamforming. ESSCIRC (2023)
Wantong Li, Xitie Zhang, Junmo Lee, F. Levent Degertekin, Shaolan Li, Shimeng Yu
Enabling Ultra-Low Power Ultrasound Imaging with Compute-in-Memory Sparse Reconstruction Accelerator. BioCAS (2023)
Dayou Wu, Guochao Peng, Yiwan Ai, Huan Li, Shaolan Li, Yating Peng
A Systematic and Innovative Six-in-One Evaluation Framework to Drive the Development of Future Hidden Champions. HCI (26) (2023)
Yuan-Chun Luo, Anni Lu, Jae Hur, Shaolan Li, Shimeng Yu
Design and Optimization of Non-Volatile Capacitive Crossbar Array for In-Memory Computing. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Jae Hur, Yuan-Chun Luo, Anni Lu, Tzu-Han Wang, Shaolan Li, Asif Islam Khan, Shimeng Yu
Nonvolatile Capacitive Crossbar Array for In-Memory Computing. Adv. Intell. Syst. 4 (8) (2022)
Tzuhan Wang, Tian Xie, Zhe Liu, Shaolan Li
-Order Noise-Shaping SAR with an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique. ISSCC (2022)
Xiyuan Tang, Jiaxin Liu, Yi Shen, Shaolan Li, Linxiao Shen, Arindam Sanyal, Kareem Ragab, Nan Sun
Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (6) (2022)
Tian Xie, Tzu-Han Wang, Zhe Liu, Shaolan Li
An 84-dB-SNDR Low-OSR Fourth-Order Noise-Shaping SAR With an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique. IEEE J. Solid State Circuits 57 (12) (2022)
Tzu-Han Wang, Ruowei Wu, Vasu Gupta, Shaolan Li
-Order Noise-Shaping SAR in a Single-Amplifier EF-CIFF Structure with Fully Dynamic Hardware-Reusing kT/C Noise Cancelation. ISSCC (2021)
Tzu-Han Wang, Ruowei Wu, Vasu Gupta, Xiyuan Tang, Shaolan Li
A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation. IEEE J. Solid State Circuits 56 (12) (2021)
Hao Chen, Mingjie Liu, Biying Xu, Keren Zhu, Xiyuan Tang, Shaolan Li, Yibo Lin, Nan Sun, David Z. Pan
MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII. IEEE Des. Test 38 (2) (2021)
Yuan-Chun Luo, Anni Lu, Jae Hur, Shaolan Li, Shimeng Yu
Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing. IMW (2021)
Yi Zhong, Xiyuan Tang, Jiaxin Liu, Wenda Zhao, Shaolan Li, Nan Sun
An 81.5dB-DR 1.25MHz-BW VCO-Based CT ΔΣ ADC with Double-PFD Quantizer. CICC (2021)
Wenda Zhao, Shaolan Li, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun
0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure. IEEE J. Solid State Circuits 55 (3) (2020)
Xiyuan Tang, Shaolan Li, Xiangxing Yang, Linxiao Shen, Wenda Zhao, Randall P. Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, David Z. Pan, Nan Sun
An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter. IEEE J. Solid State Circuits 55 (11) (2020)
Yi Zhong, Shaolan Li, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Siliang Wu, Nan Sun
A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS. IEEE J. Solid State Circuits 55 (2) (2020)
Shaolan Li, David Z. Pan, Nan Sun
An OTA-Less Second-Order VCO-Based CT $\Delta\Sigma$ Modulator Using an Inherent Passive Integrator and Capacitive Feedback. IEEE J. Solid State Circuits 55 (5) (2020)
Shaolan Li
A kT/C-Noise-Cancelled Noise-Shaping SAR ADC with a Duty-Cycled Amplifier. MWSCAS (2020)
Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, Shaolan Li, David Z. Pan, Nan Sun
A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier. IEEE J. Solid State Circuits 55 (12) (2020)
Jiaxin Liu, Chen-Kai Hsu, Xiyuan Tang, Shaolan Li, Guangjun Wen, Nan Sun
Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2019)
Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun, David Z. Pan
Device Layer-Aware Analytical Placement for Analog Circuits. ISPD (2019)
Shaolan Li, Biying Xu, David Z. Pan, Nan Sun
A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library. CICC (2019)
Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan
GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance. ICCAD (2019)
Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun, David Z. Pan
WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout. DAC (2019)
Shaolan Li, Wenda Zhao, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun
0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure. CICC (2019)
Xiyuan Tang, Shaolan Li, Linxiao Shen, Wenda Zhao, Xiangxing Yang, Randy Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, Nan Sun
A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter. ISSCC (2019)
Jiaxin Liu, Shaolan Li, Wenjuan Guo, Guangjun Wen, Nan Sun
17-fJ/Conversion-Step Third-Order CT ΔΣ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer. IEEE J. Solid State Circuits 54 (2) (2019)
Shaolan Li, Arindam Sanyal, Kyoungtae Lee, Yeonam Yoon, Xiyuan Tang, Yi Zhong, Kareem Ragab, Nan Sun
Advances in Voltage-Controlled-Oscillator-Based ΔΣ ADCs. IEICE Trans. Electron. (7) (2019)
Linxiao Shen, Yi Shen, Xiyuan Tang, Chen-Kai Hsu, Wei Shi, Shaolan Li, Wenda Zhao, Abhishek Mukherjee, Nan Sun
25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor. ISSCC (2019)
Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan
MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper. ICCAD (2019)
Linxiao Shen, Nan Sun, Yi Shen, Zhelu Li, Wei Shi, Xiyuan Tang, Shaolan Li, Wenda Zhao, Mantian Zhang, Zhangming Zhu
A Two-Step ADC With a Continuous-Time SAR-Based First Stage. IEEE J. Solid State Circuits 54 (12) (2019)
Linxiao Shen, Abhishek Mukherjee, Shaolan Li, Xiyuan Tang, Nanshu Lu, Nan Sun
A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF. VLSI Circuits (2019)
Jiaxin Liu, Shaolan Li, Wenjuan Guo, Guangjun Wen, Nan Sun
-Order Noise-Shaping SAR Quantizer. VLSI Circuits (2018)
Arindam Sanyal, Shaolan Li, Nan Sun
Low-power Scaling-friendly Ring Oscillator based ΔΣ ADC. ISCAS (2018)
Shaolan Li, Bo Qiao, Miguel Gandara, Nan Sun
-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure. ISSCC (2018)
Yi Zhong, Shaolan Li, Arindam Sanyal, Xiyuan Tang, Linxiao Shen, Siliang Wu, Nan Sun
A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS. A-SSCC (2018)
Shaolan Li, Bo Qiao, Miguel Gandara, David Z. Pan, Nan Sun
A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure. IEEE J. Solid State Circuits 53 (12) (2018)
Shaolan Li, Abhishek Mukherjee, Nan Sun
A 174.3-dB FoM VCO-Based CT ΔΣ Modulator With a Fully-Digital Phase Extended Quantizer and Tri-Level Resistor DAC in 130-nm CMOS. IEEE J. Solid State Circuits 52 (7) (2017)
Biying Xu, Shaolan Li, Xiaoqing Xu, Nan Sun, David Z. Pan
Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits. ISPD (2017)
Biying Xu, Shaolan Li, Nan Sun, David Z. Pan
A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology. DAC (2017)
Shaolan Li, Nan Sun
A 174.3dB FoM VCO-based CT ΔΣ modulator with a fully digital phase extended quantizer and tri-level resistor DAC in 130nm CMOS. ESSCIRC (2016)