Sarma Sastry

Publication Activity (10 Years)

Years Active: 1984-1993
Publications (10 Years): 0

Publications

Amitava Majumdar, Sarma Sastry
Statistical Analysis of Controllability. VLSI Design (1993)
Amitava Majumdar, Sarma Sastry
Probabilistic characterization of controllability in general homogeneous circuits. Comput. Aided Des. 25 (2) (1993)
Yung-Te Lai, Sarma Sastry, Massoud Pedram
Boolean Matching Using Binary Decision Diagrams with Applications to Logic Synthesis and Verification. ICCD (1992)
Amitava Majumdar, Sarma Sastry
On the Distribution of Fault Coverage and Test length in Random Testing of Combinational Circuits. DAC (1992)
Yung-Te Lai, Sarma Sastry
Edge-Valued Binary Decision Diagrams for Multi-Level Hierarchical Verification. DAC (1992)
Sarma Sastry, Amitava Majumdar
A Branching Process Model for Observability Analysis of Combinational Circuits. DAC (1991)
C. P. Ravikumar, Sarma Sastry
VYUHA: A detailed router for multiple routing models. Integr. 11 (2) (1991)
Sarma Sastry, Jen-I Pi
Estimating the minimum of partitioning and floorplanning problems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (2) (1991)
Sarma Sastry, Amitava Majumdar
Test efficiency analysis of random self-test of sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (3) (1991)
Ahsan Abdullah, Sarma Sastry
Topological via minimization and routing. Great Lakes Symposium on VLSI (1991)
King C. Ho, Sarma Sastry
Flexible Transistor Matrix (FTM). DAC (1991)
C. P. Ravikumar, Sarma Sastry
A hardware accelerator for hierarchical VLSI routing. Integr. 7 (3) (1989)
C. P. Ravikumar, Sarma Sastry
Parallel Placement on Hypercube Architecture. ICPP (3) (1989)
Sarma Sastry, Jen-I Pi
An Investigation into Statistical Properties of Partitioning and Floorplanning Problems. DAC (1989)
Sarma Sastry, Melvin A. Breuer
Detectability of CMOS stuck-open faults using random and pseudorandom test sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 (9) (1988)
C. P. Ravikumar, Sarma Sastry
Parallel Placement on Reduced Array Architecture. DAC (1988)
Viktor K. Prasanna, Sarma Sastry
A General Purpose VLSI Array for Efficient Signal and Image Processsing. ICPP (1987)
Sarma Sastry, Alice C. Parker
Stochastic Models for Wireability Analysis of Gate Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 (1) (1986)
Sarma Sastry, Alice C. Parker
On the relation between wire length distributions and placement of logic on master slice ICs. DAC (1984)