A hardware accelerator for hierarchical VLSI routing.
C. P. RavikumarSarma SastryPublished in: Integr. (1989)
Keyphrases
- vlsi implementation
- field programmable gate array
- single chip
- vlsi architecture
- hardware implementation
- hardware and software
- chip design
- low cost
- vlsi design
- image processing
- signal processing
- parallel hardware
- real time
- computing systems
- wireless ad hoc networks
- hierarchical model
- coarse to fine
- circuit design
- personal computer
- routing algorithm
- network topologies
- ad hoc networks
- routing protocol
- vlsi circuits
- high speed
- neural network