Rani S. Ghaida

Publication Activity (10 Years)

Years Active: 2007-2014
Publications (10 Years): 0

Top Topics

Knowledge Level

Formative Evaluation

Enabling Technology

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Rani S. Ghaida, Yasmine Badr, Puneet Gupta
Pattern-restricted design at 10nm and beyond. ICCD (2014)
Rani S. Ghaida, Yasmine Badr, Mukul Gupta, Ning Jin, Puneet Gupta
Comprehensive die-level assessment of design rules and layouts. ASP-DAC (2014)
Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta
Layout Decomposition and Legalization for Double-Patterning Technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (2) (2013)
Rani S. Ghaida, Puneet Gupta
Role of design in multiple patterning: technology development, design enablement and process control. DATE (2013)
Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars W. Liebmann, Puneet Gupta
O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction. ICICDT (2012)
Rani S. Ghaida, Puneet Gupta
DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (9) (2012)
Rani S. Ghaida, Tanaya Sahu, Parag Kulkarni, Puneet Gupta
A methodology for the early exploration of design rules for multiple-patterning technologies. ICCAD (2012)
Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta
A framework for double patterning-enabled design. ICCAD (2011)
Tuck-Boon Chan, Rani S. Ghaida, Puneet Gupta
Electrical Modeling of Lithographic Imperfections. VLSI Design (2010)
Rani S. Ghaida, Payman Zarkesh-Ha
A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow Interconnects. J. Electron. Test. 25 (1) (2009)
Rani S. Ghaida, Puneet Gupta
A framework for early and systematic evaluation of design rules. ICCAD (2009)
Rani S. Ghaida, Payman Zarkesh-Ha
Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model. DFT (2007)