Ramayya Kumar

Publication Activity (10 Years)

Years Active: 1989-1999
Publications (10 Years): 0

Publications

Ramayya Kumar
Invited Talk: Practical Use of Formal Verification - Where are we? Where do we go? VLSI Design (1999)
Sofiène Tahar, Ramayya Kumar
A Practical Methodology for the Formal Verification of RISC Processors. Formal Methods Syst. Des. 13 (2) (1998)
Dirk Eisenbiegler, Ramayya Kumar, Christian Blumenröhr
A constructive approach towards correctness of synthesis-application within retiming. ED&TC (1997)
Ramayya Kumar, Christian Blumenröhr, Dirk Eisenbiegler, Detlef Schmid
Formal Synthesis in Circuit Design - A Classification and Survey. FMCAD (1996)
Dirk Eisenbiegler, Christian Blumenröhr, Ramayya Kumar
Implementation Issues About the Embedding of Existing High Level Synthesis Algorithms in HOL. TPHOLs (1996)
Ewa Kwee-Christoph, Fridtjof Feldbusch, Ramayya Kumar, Arno Kunzmann
Generic design flows for project management in a framework environment. ED&TC (1995)
Sofiène Tahar, Ramayya Kumar
Formal Specification and Verification Techniques for RISC Pipeline Conflicts. Comput. J. 38 (2) (1995)
Dirk Eisenbiegler, Ramayya Kumar
Formally embedding existing high level synthesis algorithms. CHARME (1995)
Ramayya Kumar, Thomas Kropf, Klaus Schneider
Formal synthesis of circuits with a simple handshake protocol. VLSI Design (1995)
Dirk Eisenbiegler, Ramayya Kumar
An Automata Theory Dedicated towards Formal Circuit Synthesis. TPHOLs (1995)
Klaus Schneider, Ramayya Kumar, Thomas Kropf
Accelerating Tableaux Proofs Using Compact Representations. Formal Methods Syst. Des. 5 (1/2) (1994)
Sofiène Tahar, Ramayya Kumar
Implementational Issues for Verifying RISC-Pipeline Conflicts in HOL. TPHOLs (1994)
Klaus Schneider, Ramayya Kumar, Thomas Kropf
Automating Verification by Functional Abstraction at the System Level. TPHOLs (1994)
Klaus Schneider, Thomas Kropf, Ramayya Kumar
Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path. EDAC-ETC-EUROASIC (1994)
Ramayya Kumar, Sofiène Tahar
Formal verification of pipeline conflicts in RISC processors. EURO-DAC (1994)
Thomas Kropf, Klaus Schneider, Ramayya Kumar
A Formal Framework for High Level Synthesis. TPCD (1994)
Klaus Schneider, Ramayya Kumar, Thomas Kropf
Hardware-Verification using First Order BDDs. CHDL (1993)
Thomas Kropf, Ramayya Kumar, Klaus Schneider
Embedding Hardware Verification Within a Commercial Design Framework. CHARME (1993)
Sofiène Tahar, Ramayya Kumar
Towards a Methodology for the Formal Hierarchical Verification. ICCD (1993)
Sofiène Tahar, Ramayya Kumar
Implementing a Methodology for Formally Verifying RISC Processors in HOL. HUG (1993)
Klaus Schneider, Ramayya Kumar, Thomas Kropf
Alternative Proof Procedures for Finite-State Machines in Higher-Order Logic. HUG (1993)
Dirk Eisenbiegler, Klaus Schneider, Ramayya Kumar
A Functional Approach for Formalizing Regular Hardware Structures. HUG (1993)
Klaus Schneider, Ramayya Kumar, Thomas Kropf
Eliminating Higher-Order Quantifiers to Obtain Decision Procedures for Hardware Verification. HUG (1993)
Ramayya Kumar, Klaus Schneider, Thomas Kropf
Structuring and Automating Hardware Proofs in a Higher-Order Theorem-Proving Environment. Formal Methods Syst. Des. 2 (2) (1993)
Klaus Schneider, Ramayya Kumar, Thomas Kropf
Efficient Representation and Computation of Tableau Proofs. TPHOLs (1992)
Klaus Schneider, Ramayya Kumar, Thomas Kropf
The FAUST - Prover. CADE (1992)
Klaus Schneider, Ramayya Kumar, Thomas Kropf
Modelling Generic Hardware Structures by Abstract Datatypes. TPHOLs (1992)
Klaus Schneider, Ramayya Kumar, Thomas Kropf
Automating Most Parts of Hardware Proofs in HOL. CAV (1991)
Klaus Schneider, Ramayya Kumar, Thomas Kropf
Structure in Hardware Proofs: First Steps Towards Automation in a Higher-Order Environment. VLSI (1991)
Ramayya Kumar, Thomas Kropf, Klaus Schneider
First Steps Towards Automating Hardware Proofs in HOL. TPHOLs (1991)
Ramayya Kumar, Thomas Kropf, Klaus Schneider
Integrating a First-Order Automatic Prover in the HOL Environment. TPHOLs (1991)
Fridtjof Feldbusch, Ramayya Kumar
Verification of synthesized circuits at register transfer level with flow graphs. EURO-DAC (1991)
Thomas Wecker, Ramayya Kumar, Wolfgang Rosenstiel, Heinrich Krämer, Michael Neher
CALLAS - ein System zur automatischen Synthese digitaler Schaltungen. Inform. Forsch. Entwickl. 4 (1) (1989)