Formal verification of pipeline conflicts in RISC processors.
Ramayya KumarSofiène TaharPublished in: EURO-DAC (1994)
Keyphrases
- formal verification
- instruction set
- model checking
- parallel architecture
- application specific
- parallel algorithm
- bounded model checking
- computer architecture
- model checker
- conflict resolution
- floating point
- automated verification
- parallel processing
- resolving conflicts
- symbolic model checking
- functional verification
- embedded systems
- temporal logic
- cooperative
- program slicing
- parallel processors
- low power consumption
- domain independent
- general purpose
- software engineering