Pritish Narayanan

Publication Activity (10 Years)

Years Active: 2007-2023
Publications (10 Years): 25

Top Topics

Backpropagation Algorithm

Top Venues

Publications

Malte J. Rasch, Charles Mackin, Manuel Le Gallo, An Chen, Andrea Fasoli, Frédéric Odermatt, Ning Li, S. R. Nandakumar, Pritish Narayanan, Hsinyu Tsai, Geoffrey W. Burr, Abu Sebastian, Vijay Narayanan
Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators. CoRR (2023)
Stefano Ambrogio, Pritish Narayanan, Atsuya Okazaki, Andrea Fasoli, Charles Mackin, Kohji Hosokawa, Akiyo Nomura, Takeo Yasuda, An Chen, Alexander M. Friz, Masatoshi Ishii, Jose Luquin, Yasuteru Kohda, Nicole Saulnier, Kevin Brew, Samuel Choi, Injo Ok, Timothy Philip, Victor Chan, Mary Claire Silvestre, Ishtiaq Ahsan, Vijay Narayanan, Hsinyu Tsai, Geoffrey W. Burr
An analog-AI chip for energy-efficient speech recognition and transcription. Nat. 620 (7975) (2023)
Geoffrey W. Burr, Pritish Narayanan, Stefano Ambrogio, Atsuya Okazaki, Hsinyu Tsai, Kohji Hosokawa, Charles Mackin, Akiyo Nomura, Takeo Yasuda, J. Demarest, Kevin Brew, V. Chan, S. Choi, T. Gordon, T. M. Levin, Alexander M. Friz, Masatoshi Ishii, Yasuteru Kohda, An Chen, Andrea Fasoli, Jose Luquin, Nicole Saulnier, S. Teehan, Ishtiaq Ahsan, Vijay Narayanan
Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited). VLSI Technology and Circuits (2023)
Martin M. Frank, Ning Li, Malte J. Rasch, Shubham Jain, Ching-Tzu Chen, Ramachandran Muralidhar, Jin-Ping Han, Vijay Narayanan, Timothy Philip, Kevin Brew, Andrew Simon, Iqbal Saraf, Nicole Saulnier, Irem Boybat, Stanislaw Wozniak, Abu Sebastian, Pritish Narayanan, Charles Mackin, An Chen, Hsinyu Tsai, Geoffrey W. Burr
Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited). IRPS (2023)
Hsinyu Tsai, Pritish Narayanan, Shubham Jain, Stefano Ambrogio, Kohji Hosokawa, Masatoshi Ishii, Charles Mackin, Ching-Tzu Chen, Atsuya Okazaki, Akiyo Nomura, Irem Boybat, Ramachandran Muralidhar, Martin M. Frank, Takeo Yasuda, Alexander M. Friz, Yasuteru Kohda, An Chen, Andrea Fasoli, Malte J. Rasch, Stanislaw Wozniak, Jose Luquin, Vijay Narayanan, Geoffrey W. Burr
Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited). ISCAS (2023)
Shubham Jain, Hsinyu Tsai, Ching-Tzu Chen, Ramachandran Muralidhar, Irem Boybat, Martin M. Frank, Stanislaw Wozniak, Milos Stanisavljevic, Praneet Adusumilli, Pritish Narayanan, Kohji Hosokawa, Masatoshi Ishii, Arvind Kumar, Vijay Narayanan, Geoffrey W. Burr
A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh. IEEE Trans. Very Large Scale Integr. Syst. 31 (1) (2023)
Atsuya Okazaki, Pritish Narayanan, Stefano Ambrogio, Kohji Hosokawa, Hsinyu Tsai, Akiyo Nomura, Takeo Yasuda, Charles Mackin, Alexander M. Friz, Masatoshi Ishii, Yasuteru Kohda, Katie Spoon, An Chen, Andrea Fasoli, Malte J. Rasch, Geoffrey W. Burr
Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers. ISCAS (2022)
Kohji Hosokawa, Pritish Narayanan, Stefano Ambrogio, Hsinyu Tsai, Charles Mackin, Andrea Fasoli, Alexander M. Friz, An Chen, Jose Luquin, Katherine Spoon, Geoffrey W. Burr, Scott C. Lewis
Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI (Invited). ISCAS (2021)
Katie Spoon, Hsinyu Tsai, An Chen, Malte J. Rasch, Stefano Ambrogio, Charles Mackin, Andrea Fasoli, Alexander M. Friz, Pritish Narayanan, Milos Stanisavljevic, Geoffrey W. Burr
Toward Software-Equivalent Accuracy on Transformer-Based Deep Neural Networks With Analog Memory Devices. Frontiers Comput. Neurosci. 15 (2021)
Pritish Narayanan, Charles E. Cox, Alexis Asseman, Nicolas Antoine, Harald Huels, Winfried W. Wilcke, Ahmet S. Ozcan
Overview of the IBM Neural Computer Architecture. CoRR (2020)
Andrea Fasoli, Stefano Ambrogio, Pritish Narayanan, Hsinyu Tsai, Charles Mackin, Katherine Spoon, Alexander M. Friz, An Chen, Geoffrey W. Burr
Optimization of Analog Accelerators for Deep Neural Networks Inference. ISCAS (2020)
Charles Mackin, Pritish Narayanan, Stefano Ambrogio, Hsinyu Tsai, Katie Spoon, Andrea Fasoli, An Chen, Alexander M. Friz, Robert M. Shelby, Geoffrey W. Burr
Neuromorphic Computing with Phase Change, Device Reliability, and Variability Challenges. IRPS (2020)
Stefano Ambrogio, Pritish Narayanan, Hsinyu Tsai, Charles Mackin, Katherine Spoon, An Chen, Andrea Fasoli, Alexander M. Friz, Geoffrey W. Burr
Accelerating Deep Neural Networks with Analog Memory Devices. AICAS (2020)
Alessandro Fumarola, Yusuf Leblebici, Pritish Narayanan, Robert M. Shelby, L. L. Sanchez, Geoffrey W. Burr, Kibong Moon, J. Jang, Hyunsang Hwang, Severin Sidler
Non-filamentary non-volatile memory elements as synapses in neuromorphic systems. NVMTS (2019)
Massimo Giordano, Giorgio Cristiano, Koji Ishibashi, Stefano Ambrogio, Hsinyu Tsai, Geoffrey W. Burr, Pritish Narayanan
Analog-to-Digital Conversion With Reconfigurable Function Mapping for Neural Networks Activation Function Acceleration. IEEE J. Emerg. Sel. Topics Circuits Syst. 9 (2) (2019)
Hung-Yang Chang, Pritish Narayanan, Scott C. Lewis, Nathan C. P. Farinha, Kohji Hosokawa, Charles Mackin, Hsinyu Tsai, Stefano Ambrogio, An Chen, Geoffrey W. Burr
AI hardware acceleration with analog memory: Microarchitectures for low energy at high speed. IBM J. Res. Dev. 63 (6) (2019)
Stefano Ambrogio, Pritish Narayanan, Hsinyu Tsai, Robert M. Shelby, Irem Boybat, Carmelo di Nolfo, Severin Sidler, Massimo Giordano, Martina Bodini, Nathan C. P. Farinha, Benjamin Killeen, Christina Cheng, Yassine Jaoudi, Geoffrey W. Burr
Equivalent-accuracy accelerated neural-network training using analogue memory. Nat. 558 (7708) (2018)
Koji Inoue, Takuya Araki, Takumi Maruyama, Pritish Narayanan, Takashi Oshima, Martin Schulz
Panel discussions: "Challenges to the scaling limits: How can we achieve sustainable power-performance improvements?". COOL CHIPS (2018)
Irem Boybat, Carmelo di Nolfo, Stefano Ambrogio, Martina Bodini, Nathan C. P. Farinha, Robert M. Shelby, Pritish Narayanan, Severin Sidler, Hsinyu Tsai, Yusuf Leblebici, Geoffrey W. Burr
Improved Deep Neural Network Hardware-Accelerators Based on Non-Volatile-Memory: The Local Gains Technique. ICRC (2017)
Pritish Narayanan, Lucas L. Sanches, Alessandro Fumarola, Robert M. Shelby, Stefano Ambrogio, Jun-Woo Jang, Hyunsang Hwang, Yusuf Leblebici, Geoffrey W. Burr
Reducing circuit design complexity for neuromorphic machine learning systems based on Non-Volatile Memory arrays. ISCAS (2017)
Pritish Narayanan, Alessandro Fumarola, Lucas L. Sanches, Kohji Hosokawa, Scott C. Lewis, Robert M. Shelby, Geoffrey W. Burr
Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory. IBM J. Res. Dev. 61 (4-5) (2017)
Geoffrey W. Burr, Pritish Narayanan, Robert M. Shelby, Stefano Ambrogio, Hsinyu Tsai, Scott L. Lewis, Kohji Hosokawa
Neuromorphic devices and architectures for next-generation cognitive computing. ISCAS (2017)
Alessandro Fumarola, Pritish Narayanan, Lucas L. Sanches, Severin Sidler, Jun-Woo Jang, Kibong Moon, Robert M. Shelby, Hyunsang Hwang, Geoffrey W. Burr
Accelerating machine learning with Non-Volatile Memory: Exploring device and circuit tradeoffs. ICRC (2016)
Severin Sidler, Irem Boybat, Robert M. Shelby, Pritish Narayanan, Jun-Woo Jang, Alessandro Fumarola, Kibong Moon, Yusuf Leblebici, Hyunsang Hwang, Geoffrey W. Burr
Large-scale neural networks implemented with Non-Volatile Memory as the synaptic weight element: Impact of conductance response. ESSDERC (2016)
Pritish Narayanan, Geoffrey W. Burr, Kumar Virwani, Bülent N. Kurdi
Circuit-Level Benchmarking of Access Devices for Resistive Nonvolatile Memory Arrays. IEEE J. Emerg. Sel. Topics Circuits Syst. 6 (3) (2016)
Suyog Gupta, Ankur Agrawal, Kailash Gopalakrishnan, Pritish Narayanan
Deep Learning with Limited Numerical Precision. CoRR (2015)
Suyog Gupta, Ankur Agrawal, Kailash Gopalakrishnan, Pritish Narayanan
Deep Learning with Limited Numerical Precision. ICML (2015)
Mostafizur Rahman, Pritish Narayanan, Csaba Andras Moritz
Metal-Gated Junctionless Nanowire Transistors. CoRR (2014)
Csaba Andras Moritz, Santosh Khasanvis, Pritish Narayanan
Introduction to JPDC special issue on computing with future nanotechnology. J. Parallel Distributed Comput. 74 (6) (2014)
Jianfeng Zhang, Mostafizur Rahman, Pritish Narayanan, Santosh Khasanvis, Csaba Andras Moritz
Parameter variation sensing and estimation in nanoscale fabrics. J. Parallel Distributed Comput. 74 (6) (2014)
Santosh Khasanvis, Mostafizur Rahman, Prasad Shabadi, Pritish Narayanan, Hyung Suk Yu, Chi On Chui, Csaba Andras Moritz
Nanowire field-programmable computing platform. NANOARCH (2013)
Pritish Narayanan, Michael Leuchtenburg, Jorge Kina, Prachi Joshi, Pavan Panchapakeshan, Chi On Chui, Csaba Andras Moritz
Variability in Nanoscale Fabrics: Bottom-up Integrated Analysis and Mitigation. ACM J. Emerg. Technol. Comput. Syst. 9 (1) (2013)
Mostafizur Rahman, Pritish Narayanan, Santosh Khasanvis, John Nicholson, Csaba Andras Moritz
Experimental prototyping of beyond-CMOS nanowire computing fabrics. NANOARCH (2013)
Santosh Khasanvis, K. M. Masum Habib, Mostafizur Rahman, Pritish Narayanan, Roger K. Lake, Csaba Andras Moritz
Ternary volatile random access memory based on heterogeneous graphene-CMOS fabric. NANOARCH (2012)
Santosh Khasanvis, K. M. Masum Habib, Mostafizur Rahman, Pritish Narayanan, Roger K. Lake, Csaba Andras Moritz
Hybrid Graphene Nanoribbon-CMOS tunneling volatile memory fabric. NANOARCH (2011)
Md. Muwyid U. Khan, Pritish Narayanan, Priyamvada Vijayakumar, Israel Koren, C. Mani Krishna, Csaba Andras Moritz
Biased Voting for Improved Yield in Nanoscale Fabrics. DFT (2011)
Pavan Panchapakeshan, Pritish Narayanan, Csaba Andras Moritz
N3ASICs: Designing nanofabrics with fine-grained CMOS integration. NANOARCH (2011)
Ciprian Teodorov, Pritish Narayanan, Loïc Lagadec, Catherine Dezan
Regular 2D NASIC-based architecture and design space exploration. NANOARCH (2011)
Yao Guo, Pritish Narayanan, Mahmoud A. Bennaser, Saurabh Chheda, Csaba Andras Moritz
Energy-Efficient Hardware Data Prefetching. IEEE Trans. Very Large Scale Integr. Syst. 19 (2) (2011)
Priyamvada Vijayakumar, Pritish Narayanan, Israel Koren, C. Mani Krishna, Csaba Andras Moritz
Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics. NANOARCH (2011)
Pritish Narayanan, Jorge Kina, Pavan Panchapakeshan, Priyamvada Vijayakumar, Kyeong-Sik Shin, Mostafizur Rahman, Michael Leuchtenburg, Israel Koren, Chi On Chui, Csaba Andras Moritz
Nanoscale Application Specific Integrated Circuits. NANOARCH (2011)
Prasad Shabadi, Alexander Khitun, Pritish Narayanan, Mingqiang Bao, Israel Koren, Kang L. Wang, Csaba Andras Moritz
Towards logic functions as the device. NANOARCH (2010)
Priyamvada Vijayakumar, Pritish Narayanan, Israel Koren, C. Mani Krishna, Csaba Andras Moritz
Incorporating Heterogeneous Redundancy in a Nanoprocessor for Improved Yield and Performance. DFT (2010)
Pritish Narayanan, Michael Leuchtenburg, Jorge Kina, Prachi Joshi, Pavan Panchapakeshan, Chi On Chui, Csaba Andras Moritz
Parameter Variability in Nanoscale Fabrics: Bottom-Up Integrated Exploration. DFT (2010)
Pritish Narayanan, Teng Wang, Csaba Andras Moritz
Programmable cellular architectures at the nanoscale. Nano Commun. Networks 1 (2) (2010)
Pritish Narayanan, Csaba Andras Moritz, Kyoung-won Park, Chi On Chui
Validating cascading of crossbar circuits with an integrated device-circuit exploration. NANOARCH (2009)
Catherine Dezan, Ciprian Teodorov, Loïc Lagadec, Michael Leuchtenburg, Teng Wang, Pritish Narayanan, Csaba Andras Moritz
Towards a framework for designing applications onto hybrid nano/CMOS fabrics. Microelectron. J. 40 (4-5) (2009)
Pritish Narayanan, Michael Leuchtenburg, Teng Wang, Csaba Andras Moritz
CMOS Control Enabled Single-Type FET NASIC. ISVLSI (2008)
Michael Leuchtenburg, Pritish Narayanan, Teng Wang, Csaba Andras Moritz
Impact of Process Variation in Fault-Resilient Streaming Nanoprocessors. NanoNet (2008)
Teng Wang, Pritish Narayanan, Csaba Andras Moritz
Combining 2-level logic families in grid-based nanoscale fabrics. NANOARCH (2007)
Csaba Andras Moritz, Teng Wang, Pritish Narayanan, Michael Leuchtenburg, Yao Guo, Catherine Dezan, Mahmoud A. Bennaser
Fault-Tolerant Nanoscale Processors on Semiconductor Nanowire Grids. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2007)