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Chi On Chui
Publication Activity (10 Years)
Years Active: 2005-2016
Publications (10 Years): 2
Top Topics
Multiobjective Optimization
Computing Platform
Lower Level
Palmprint
Top Venues
IEEE Trans. Very Large Scale Integr. Syst.
ASP-DAC
NANOARCH
ACM J. Emerg. Technol. Comput. Syst.
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Publications
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Shaodi Wang
,
Andrew Pan
,
Chi On Chui
,
Puneet Gupta
PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices.
IEEE Trans. Very Large Scale Integr. Syst.
24 (1) (2016)
Greg Leung
,
Shaodi Wang
,
Andrew Pan
,
Puneet Gupta
,
Chi On Chui
An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
24 (5) (2016)
Shaodi Wang
,
Andrew Pan
,
Chi On Chui
,
Puneet Gupta
PROCEED: A pareto optimization-based circuit-level evaluator for emerging devices.
ASP-DAC
(2014)
Santosh Khasanvis
,
Mostafizur Rahman
,
Prasad Shabadi
,
Pritish Narayanan
,
Hyung Suk Yu
,
Chi On Chui
,
Csaba Andras Moritz
Nanowire field-programmable computing platform.
NANOARCH
(2013)
Pritish Narayanan
,
Michael Leuchtenburg
,
Jorge Kina
,
Prachi Joshi
,
Pavan Panchapakeshan
,
Chi On Chui
,
Csaba Andras Moritz
Variability in Nanoscale Fabrics: Bottom-up Integrated Analysis and Mitigation.
ACM J. Emerg. Technol. Comput. Syst.
9 (1) (2013)
Pritish Narayanan
,
Jorge Kina
,
Pavan Panchapakeshan
,
Priyamvada Vijayakumar
,
Kyeong-Sik Shin
,
Mostafizur Rahman
,
Michael Leuchtenburg
,
Israel Koren
,
Chi On Chui
,
Csaba Andras Moritz
Nanoscale Application Specific Integrated Circuits.
NANOARCH
(2011)
Pritish Narayanan
,
Michael Leuchtenburg
,
Jorge Kina
,
Prachi Joshi
,
Pavan Panchapakeshan
,
Chi On Chui
,
Csaba Andras Moritz
Parameter Variability in Nanoscale Fabrics: Bottom-Up Integrated Exploration.
DFT
(2010)
Pritish Narayanan
,
Csaba Andras Moritz
,
Kyoung-won Park
,
Chi On Chui
Validating cascading of crossbar circuits with an integrated device-circuit exploration.
NANOARCH
(2009)
Hai Lan
,
Tze Wee Chen
,
Chi On Chui
,
Parastoo Nikaeen
,
Jae Wook Kim
,
Robert W. Dutton
Synthesized Compact Models and Experimental Verifications for Substrate Noise Coupling in Mixed-Signal ICs.
IEEE J. Solid State Circuits
41 (8) (2006)
Hai Lan
,
Tze Wee Chen
,
Chi On Chui
,
Parastoo Nikaeen
,
Jae Wook Kim
,
Robert W. Dutton
Synthesized compact model and experimental results for substrate noise coupling in lightly doped processes.
CICC
(2005)