Pranay Prabhat

Publication Activity (10 Years)

Years Active: 2015-2023
Publications (10 Years): 14

Top Topics

Memory Footprint

Fully Integrated

Top Venues

IEEE J. Solid State Circuits

Publications

Sivert T. Sliper, William Wang, Nikos Nikoleris, Alex S. Weddell, Anand Savanth, Pranay Prabhat, Geoff V. Merrett
Pragmatic Memory-System Support for Intermittent Computing Using Emerging Nonvolatile Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (1) (2023)
Fernando García-Redondo, Pranay Prabhat, Mudit Bhargava, Cyrille Dray
A Compact Model for Scalable MTJ Simulation. CoRR (2021)
Benoît Labbé, Philex Ming-Yan Fan, Thanusree Achuthan, Pranay Prabhat, Graham Knight, James Myers
A Supply Voltage Control Method for Performance Guaranteed Ultra-Low-Power Microcontroller. IEEE J. Solid State Circuits 56 (2) (2021)
Fernando García-Redondo, Pranay Prabhat, Mudit Bhargava
A Fokker-Planck Solver to Model MTJ Stochasticity. ESSDERC (2021)
Fernando García-Redondo, Pranay Prabhat, Mudit Bhargava
A Fokker-Planck Solver to Model MTJ Stochasticity. CoRR (2021)
Pranay Prabhat, Benoît Labbé, Graham Knight, Anand Savanth, Jonas Svedas, Matthew J. Walker, Supreet Jeloka, Philex Ming-Yan Fan, Fernando García-Redondo, Thanusree Achuthan, James Myers
27.2 M0N0: A Performance-Regulated 0.8-to-38MHz DVFS ARM Cortex-M33 SIMD MCU with 10nW Sleep Power. ISSCC (2020)
Philex Ming-Yan Fan, Anand Savanth, Benoît Labbé, Pranay Prabhat, James Myers
A 0.98-nW/kHz 33-kHz Fully Integrated Subthreshold-Region Operation RC Oscillator With Forward-Body-Biasing. ESSCIRC (2019)
Supreet Jeloka, Pranay Prabhat, Graham Knight, James Myers
A 65nm switched source line sub-threshold ROM using data encoding, with 0.3V Vmin and 47fJ/b access energy. ISLPED (2019)
Yunpeng Cai, Anand Savanth, Pranay Prabhat, James Myers, Alex S. Weddell, Tom J. Kazmierski
Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS. IEEE J. Solid State Circuits 54 (2) (2019)
Pranay Prabhat, Graham Knight, Supreet Jeloka, Sheng Yang, James Myers
A bulk 65nm Cortex-M0+ SoC with All-Digital Forward Body Bias for 4.3X Subthreshold Speedup. A-SSCC (2018)
Yunpeng Cai, Anand Savanth, Pranay Prabhat, James Myers, Alex S. Weddell, Tom J. Kazmierski
Evaluation and analysis of single-phase clock flip-flops for NTV applications. PATMOS (2017)
Jordan Morris, Pranay Prabhat, James Myers, Alex Yakovlev
Unconventional Layout Techniques for a High Performance, Low Variability Subthreshold Standard Cell Library. ISVLSI (2017)
James Myers, Pranay Prabhat, Anand Savanth, Sheng Yang, Rohan Gaddh
Design challenges for near and sub-threshold operation: A case study with an ARM Cortex-M0+ based WSN subsystem. PATMOS (2016)
James Myers, Anand Savanth, Rohan Gaddh, David Howard, Pranay Prabhat, David Flynn
A Subthreshold ARM Cortex-M0+ Subsystem in 65 nm CMOS for WSN Applications with 14 Power Domains, 10T SRAM, and Integrated Voltage Regulator. IEEE J. Solid State Circuits 51 (1) (2016)
James Myers, Anand Savanth, David Howard, Rohan Gaddh, Pranay Prabhat, David Flynn
8.1 An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65nm CMOS for WSN applications. ISSCC (2015)