Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS.
Yunpeng CaiAnand SavanthPranay PrabhatJames MyersAlex S. WeddellTom J. KazmierskiPublished in: IEEE J. Solid State Circuits (2019)
Keyphrases
- low power
- ultra low power
- single phase
- cmos technology
- power dissipation
- flip flops
- power consumption
- high speed
- nm technology
- low cost
- control algorithm
- power supply
- single chip
- low voltage
- input output
- control method
- pulse width modulation
- active power filter
- digital signal processing
- image sensor
- neural network
- power electronics
- silicon on insulator
- leakage current
- pattern recognition