Péter Földesy

Publication Activity (10 Years)

Years Active: 1997-2020
Publications (10 Years): 2

Top Topics

Intensive Care Units

Foreground Detection

Top Venues

J. Syst. Archit.

Publications

Ákos Zarándy, Péter Földesy, Ádám Nagy, Imre Jánoki, Dániel Terbe, Máté Siket, Miklós Szabó, Judit Varga
Multi-Level Optimization for Enabling Life Critical Visual Inspections of Infants in Resource Limited Environment. ISCAS (2020)
Péter Földesy, Imre Jánoki, Ákos Zarándy, Péter Pázmány
Non-Contact Vital-Sign Monitoring System for Premature Infants in Neonatal Intensive Care Units. ERCIM News 2020 (122) (2020)
Ricardo Carmona-Galán, Ákos Zarándy, Csaba Rekeczky, Péter Földesy, Alberto Rodríguez-Pérez, Carlos M. Domínguez-Matas, Jorge Fernández-Berni, Gustavo Liñán Cembrano, Maria Belen Pérez-Verdú, Zoltán Kárász, Manuel Suárez-Cambre, Víctor Manuel Brea Sánchez, Tamás Roska, Ángel Rodríguez-Vázquez
A hierarchical vision processing architecture oriented to 3D integration of smart camera chips. J. Syst. Archit. 59 (10-A) (2013)
Péter Földesy, Domonkos Gergelyi, Csaba Fuzy, Gergely Károlyi
Test and configuration architecture of a sub-THz CMOS detector array. DDECS (2012)
Péter Földesy
Characterization of silicon field effect transistor sub-THz detectors for imaging systems. ISCAS (2012)
Péter Földesy, Ricardo Carmona-Galán, Ákos Zarándy, Csaba Rekeczky, Ángel Rodríguez-Vázquez, Tamás Roska
3D multi-layer vision architecture for surveillance and reconnaissance applications. ECCTD (2009)
Péter Földesy, Ákos Zarándy, Csaba Rekeczky
Configurable 3D-integrated focal-plane cellular sensor-processor array architecture. Int. J. Circuit Theory Appl. 36 (5-6) (2008)
Péter Földesy, Ákos Zarándy, Csaba Rekeczky, Tamás Roska
3D integrated scalable focal-plane processor array. ECCTD (2007)
Péter Földesy, Ákos Zarándy, Csaba Rekeczky, Tamás Roska
High performance processor array for image processing. ISCAS (2007)
Péter Földesy, Ákos Zarándy, Csaba Rekeczky, Tamás Roska
Digital implementation of cellular sensor-computers. Int. J. Circuit Theory Appl. 34 (4) (2006)
Ákos Zarándy, Péter Földesy, Péter Szolgay, Szabolcs Tõkés, Csaba Rekeczky, Tamás Roska
Various implementations of topographic, sensory, cellular wave computers. ISCAS (6) (2005)
Ákos Zarándy, Péter Földesy, Tamás Roska
Per-pixel integration time controlled image sensor. ECCTD (2005)
Ákos Zarándy, Csaba Rekeczky, Péter Földesy, István Szatmári
The New Framework Of Applications: The Aladdin System. J. Circuits Syst. Comput. 12 (6) (2003)
György Cserey, Csaba Rekeczky, Péter Földesy
PDE-Based Histogram Modification With Embedded Morphological Processing Of The Level-Sets. J. Circuits Syst. Comput. 12 (4) (2003)
Péter Földesy, Ángel Rodríguez-Vázquez
A behavioural modelling technique for visual microprocessor mixed-signal VLSI chips. Int. J. Circuit Theory Appl. 30 (2-3) (2002)
Csaba Rekeczky, István Szatmári, Péter Földesy
Computing on silicon with trigger waves: experiments on CNN-UM chips. ISCAS (3) (2001)
István Szatmári, Ákos Zarándy, Péter Földesy, László Kék
An analogic CNN engine board with the 64×64 analog I/O CNN-UM chip. ISCAS (2000)
Gustavo Liñán, Péter Földesy, A. Rodrignez-Vazquez, Servando Espejo, Rafael Domínguez-Castro
Implementation of non-linear templates using a decomposition technique by a 0.5 μm CMOS CNN universal chip. ISCAS (2000)
Rafael Domínguez-Castro, Servando Espejo, Ángel Rodríguez-Vázquez, Ricardo Carmona, Péter Földesy, Ákos Zarándy, Péter Szolgay, Tamás Szirányi, Tamás Roska
A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage. IEEE J. Solid State Circuits 32 (7) (1997)