Test and configuration architecture of a sub-THz CMOS detector array.
Péter FöldesyDomonkos GergelyiCsaba FuzyGergely KárolyiPublished in: DDECS (2012)
Keyphrases
- high speed
- focal plane
- analog vlsi
- management system
- charge coupled device
- image sensor
- detection method
- low cost
- real time
- software architecture
- power consumption
- processor array
- analog to digital converter
- infrared
- detection algorithm
- nm technology
- random access memory
- statistical tests
- linear array
- optimal configuration
- hardware architecture
- design considerations
- low power
- test cases
- object detection
- neural network