Nobuki Kajihara

Publication Activity (10 Years)

Years Active: 1988-2024
Publications (10 Years): 1

Top Topics

Fpga Implementation

Reservoir Computing

Global Constraints

Maximum Likelihood Estimation

Top Venues

Publications

Shigeki Matsumoto, Yuki Ichikawa, Nobuki Kajihara, Hakaru Tamukoh
FPGA Implementation for Large Scale Reservoir Computing based on Chaotic Boltzmann Machine. ISCAS (2024)
Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara
Arithmetic Operation Oriented Reconfigurable Chip: RHW. FPL (2001)
Masaya Iwata, Isamu Kajitani, Yong Liu, Nobuki Kajihara, Tetsuya Higuchi
Implementation of a Gate-Level Evolvable Hardware Chip. ICES (2001)
Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara
Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW. FCCM (2000)
Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Xin Yao, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi
The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing. IEEE Trans. Computers 48 (6) (1999)
Isamu Kajitani, Tsutomu Hoshino, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi
An Evolvable Hardware Chip and Its Application as a Multi-Function Prosthetic Hand Controller. AAAI/IAAI (1999)
Isamu Kajitani, Masahiro Murakawa, Nobuki Kajihara, Masaya Iwata, Hidenori Sakanashi, Tetsuya Higuchi
Evolvable Hardware Chips for Neural Network Applications. ICANNGA (1999)
Tetsuya Higuchi, Nobuki Kajihara
Evolvable Hardware Chips for Industrial Applications. Commun. ACM 42 (4) (1999)
Tetsuya Higuchi, Masaya Iwata, Didier Keymeulen, Hidenori Sakanashi, Masahiro Murakawa, Isamu Kajitani, Eiichi Takahashi, Kenji Toda, Mehrdad Salami, Nobuki Kajihara, Nobuyuki Otsu
Real-world applications of analog and digital evolvable hardware . IEEE Trans. Evol. Comput. 3 (3) (1999)
Hidenori Sakanashi, Mehrdad Salami, Masaya Iwata, Shogo Nakaya, Tsukasa Yamauchi, Takeshi Inuo, Nobuki Kajihara, Tetsuya Higuchi
Evolvable Hardware Chip for High Precision Printer Image Compression. AAAI/IAAI (1998)
Isamu Kajitani, Tsutomu Hoshino, Daisuke Nishikawa, Hiroshi Yokoi, Shogo Nakaya, Tsukasa Yamauchi, Takeshi Inuo, Nobuki Kajihara, Masaya Iwata, Didier Keymeulen, Tetsuya Higuchi
A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI. ICES (1998)
Tsukasa Yamauchi, Shogo Nakaya, Nobuki Kajihara
SOP: a reconfigurable massively parallel system and its control-data-flow based compiling method. FCCM (1996)
Tsukasa Yamauchi, Shogo Nakaya, Nobuki Kajihara
SOP: An Adaptive Massively Parallel Computer and its Control-Data-Flow Based Compiling Method. Parcella (1996)
Nobuhiko Koike, Toshiyuki Nakata, Nobuki Kajihara
MAN-YO: Mixed level parallel logic simulation engine. Systems and Computers in Japan 20 (10) (1989)
Nobuki Kajihara, Satoshi Matsushita, Toshiyuki Nakata, Nobuhiko Koike
Parallel neural network simulation machine: Neuman. Neural Networks 1 (Supplement-1) (1988)