Arithmetic Operation Oriented Reconfigurable Chip: RHW.

Tsukasa Yamauchi Shogo Nakaya Takeshi Inuo Nobuki Kajihara

Published in: FPL (2001)

Keyphrases

low cost
micron cmos
high speed
arithmetic operations
reconfigurable architecture
functional units
single chip
real time
reconfigurable hardware
systolic array
neural network
data sets
floating point
evolvable hardware
vlsi design
genetic algorithm
charge coupled devices