Nitin Chaturvedi

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 13

Top Topics

Delay Insensitive

Replication Scheme

Top Venues

Publications

Kartik Jhawar, Jugal Gandhi, Diksha Shekhawat, Aniket Upadhyay, Avadh Harkishanka, Nitin Chaturvedi, M. Santosh, Jai Gopal Pandey
Modeling, hardware architecture, and performance analyses of an AEAD-based lightweight cipher. J. Real Time Image Process. 21 (2) (2024)
Kanika Monga, Eesha Karnawat, Nitin Chaturvedi, S. Gurunarayanan
Design of a Programmable Delay Line with On-Chip Calibration to Achieve Immunity Against Process Variations. VDAT (2022)
Kanika Monga, Kunal Harbhajanka, Arush Srivastava, Nitin Chaturvedi, S. Gurunarayanan
Design of an MTJ/CMOS-Based Asynchronous System for Ultra-Low Power Energy Autonomous Applications. J. Circuits Syst. Comput. 30 (4) (2021)
Tejasvi Alladi, Vishnu Venkatesh, Vinay Chamola, Nitin Chaturvedi
Drone-MAP: A Novel Authentication Scheme for Drone-Assisted 5G Networks. INFOCOM Workshops (2021)
Kanika Monga, Lakshaya Maheshwari, Nitin Chaturvedi, S. Gurunarayanan
Twin-Coupled Sense Amplifier to improve margin in 1T-1MTJ based MRAM array. VDAT (2020)
Kanika Monga, Akul Malhotra, Nitin Chaturvedi, S. Gurunayaranan
A Novel Low Power Non-Volatile SRAM Cell with Self Write Termination. ICCCNT (2019)
Kanika Monga, Akul Malhotra, Nitin Chaturvedi, S. Gurunayaranan
A Novel Low Power Non-Volatile SRAM Cell with Self Write Termination. CoRR (2019)
Kanika Monga, Nitin Chaturvedi
A CMOS/MTJ Based Novel Non-volatile SRAM Cell with Asynchronous Write Termination for Normally OFF Applications. VDAT (2019)
Kanika, R. Sankara Prasad, Nitin Chaturvedi, S. Gurunarayanan
A low power high speed MTJ based non-volatile SRAM cell for energy harvesting based IoT applications. Integr. 65 (2019)
R. Gautham Sundar Ram, Nitin Chaturvedi, Sumeet Saurav, Sanjay Singh
An FPGA Based Hardware Accelerator for Classification of Handwritten Digits. ISDA (1) (2018)
Pranshu Kalra, Shaista Hussain, Nitin Chaturvedi
An Investigation of Power-Performance Aware Accelerator/Core Allocation Challenges in Dark Silicon Heterogeneous Systems. iNIS (2016)
Nitin Chaturvedi, S. Gurunarayanan
An efficient adaptive block pinning for multicore architectures. Microprocess. Microsystems 39 (3) (2015)
Nitin Chaturvedi, Arun Subramaniyan, S. Gurunarayanan
An adaptive migration-replication scheme (AMR) for shared cache in chip multiprocessors. J. Supercomput. 71 (10) (2015)