An FPGA Based Hardware Accelerator for Classification of Handwritten Digits.
R. Gautham Sundar RamNitin ChaturvediSumeet SauravSanjay SinghPublished in: ISDA (1) (2018)
Keyphrases
- handwritten digits
- field programmable gate array
- hardware implementation
- low cost
- character recognition
- real time
- feature vectors
- decision trees
- support vector
- hardware architecture
- image classification
- machine learning
- hardware design
- orl face
- massively parallel
- parallel implementation
- computing systems
- embedded systems
- class labels
- text categorization
- support vector machine
- object recognition