S. Gurunarayanan

Publication Activity (10 Years)

Years Active: 2006-2022
Publications (10 Years): 8

Top Topics

Replication Scheme

Wireless Sensor Networks

Top Venues

Future Gener. Comput. Syst.

Publications

Kanika Monga, Eesha Karnawat, Nitin Chaturvedi, S. Gurunarayanan
Design of a Programmable Delay Line with On-Chip Calibration to Achieve Immunity Against Process Variations. VDAT (2022)
Kanika Monga, Kunal Harbhajanka, Arush Srivastava, Nitin Chaturvedi, S. Gurunarayanan
Design of an MTJ/CMOS-Based Asynchronous System for Ultra-Low Power Energy Autonomous Applications. J. Circuits Syst. Comput. 30 (4) (2021)
Kanika Monga, Lakshaya Maheshwari, Nitin Chaturvedi, S. Gurunarayanan
Twin-Coupled Sense Amplifier to improve margin in 1T-1MTJ based MRAM array. VDAT (2020)
G. Sai Sesha Chalapathi, Vinay Chamola, Chen-Khong Tham, S. Gurunarayanan, Nirwan Ansari
An optimal delay aware task assignment scheme for wireless SDN networked edge cloudlets. Future Gener. Comput. Syst. 102 (2020)
G. Sai Sesha Chalapathi, Vinay Chamola, S. Gurunarayanan
A testbed validated simple time synchronization protocol for clustered wireless sensor networks for IoT. J. Intell. Fuzzy Syst. 36 (5) (2019)
G. Sai Sesha Chalapathi, Bernhard Etzlinger, S. Gurunarayanan, Andreas Springer
Integrated Cooperative Synchronization for Wireless Sensor Networks. IEEE Wirel. Commun. Lett. 8 (3) (2019)
Kanika, R. Sankara Prasad, Nitin Chaturvedi, S. Gurunarayanan
A low power high speed MTJ based non-volatile SRAM cell for energy harvesting based IoT applications. Integr. 65 (2019)
D. C. Kiran, S. Gurunarayanan, Janardan Prasad Misra, Munish Bhatia
Register allocation for fine grain threads on multicore processor. J. King Saud Univ. Comput. Inf. Sci. 29 (1) (2017)
Nitin Chaturvedi, S. Gurunarayanan
An efficient adaptive block pinning for multicore architectures. Microprocess. Microsystems 39 (3) (2015)
Nitin Chaturvedi, Arun Subramaniyan, S. Gurunarayanan
An adaptive migration-replication scheme (AMR) for shared cache in chip multiprocessors. J. Supercomput. 71 (10) (2015)
Jai Gopal Pandey, Arindam Karmakar, Chandra Shekhar, S. Gurunarayanan
An FPGA-Based Architecture for Local Similarity Measure for Image/Video Processing Applications. VLSI Design (2015)
D. C. Kiran, S. Gurunarayanan, Janardan Prasad Misra, Abhijeet Nawal
Global Scheduling Heuristics for Multicore Architecture. Sci. Program. 2015 (2015)
Jai Gopal Pandey, Arindam Karmakar, Chandra Shekhar, S. Gurunarayanan
An embedded framework for accurate object localization using center of gravity measure with mean shift procedure. VDAT (2015)
Jai Gopal Pandey, Arindam Karmakar, Chandra Shekhar, S. Gurunarayanan
A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm. VLSI Design (2014)
Jai Gopal Pandey, Arindam Karmakar, S. Gurunarayanan
Architectures and algorithms for image and video processing using FPGA-based platform. VDAT (2014)
Munish Bhatia, D. C. Kiran, Janardan Prasad Misra, S. Gurunarayanan
Fine grain thread scheduling on multicore processors: cores with multiple functional units. COMPUTE (2013)
D. C. Kiran, S. Gurunarayanan, Janardan Prasad Misra, Faizan Khaliq
An efficient method to compute static single assignment form for multicore architecture. RAIT (2012)
Biju K. Raveendran, Sundar Balasubramaniam, S. Gurunarayanan
Evaluation of priority based real time scheduling algorithms: choices and tradeoffs. SAC (2008)
Biju K. Raveendran, T. S. B. Sudarshan, Avinash Patil, Komal B. Randive, S. Gurunarayanan
An Energy Efficient Selective Placement Scheme for Set-Associative Data Cache in Embedded System. ESA (2007)
Biju K. Raveendran, Janardan Prasad Misra, Karan Bhatnagar, S. Gurunarayanan
EFFS: Efficient Flash File System for Wireless Sensor Nodes. ESA (2007)
Biju K. Raveendran, K. Durga Prasad, Sundar Balasubramaniam, S. Gurunarayanan
Variants of Priority Scheduling Algorithms for Reducing Context-Switches in Real-Time Systems. ICDCN (2006)
Biju K. Raveendran, Sundar Balasubramaniam, K. Durga Prasad, S. Gurunarayanan
A Context-Switch Reduction Heuristic for Power-Aware Off-Line Scheduling. Asia-Pacific Computer Systems Architecture Conference (2006)