Biju K. Raveendran

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 14

Top Topics

Energy Efficient

Scheduling Algorithm

Memory Hierarchy

Embedded Processors

Top Venues

Int. J. Embed. Syst.

Int. J. Parallel Emergent Distributed Syst.

Publications

Arun S. Nair, Geeta Patil, Archit Agarwal, Aboli Vijayan Pai, Biju K. Raveendran, Sasikumar Punnekkat
CAMP: a hierarchical cache architecture for multi-core mixed criticality processors. Int. J. Parallel Emergent Distributed Syst. 39 (3) (2024)
Louella Colaco, Arun S. Nair, Biju K. Raveendran, Sasikumar Punnekkat
Task models for mixed criticality systems - a review. Int. J. Crit. Comput. Based Syst. 10 (4) (2023)
Louella Colaco, Prashiksha Jain, Arun S. Nair, Biju K. Raveendran, Sasikumar Punnekkat
mcDVFS: cycle conserving DVFS scheduler for multi-core mixed criticality systems. Int. J. Parallel Emergent Distributed Syst. 38 (5) (2023)
Louella Colaco, Arun S. Nair, Anurag Madnawat, Biju K. Raveendran
SACRED: Software Approach for Collaboration and Research Dissemination. Int. J. e Collab. 19 (1) (2023)
Louella Colaco, Amol Pai, Biju K. Raveendran, Sasikumar Punnekkat
pmcEDF: An Energy Efficient Procrastination Scheduler for Multi-core Mixed Criticality Systems. HPCC/DSS/SmartCity/DependSys (2021)
Arun S. Nair, Aboli Vijayan Pai, Biju K. Raveendran, Geeta Patil
MOESIL: A Cache Coherency Protocol for Locked Mixed Criticality L1 Data Cache. DS-RT (2021)
Arun S. Nair, Louella Mesquita Colaco, Geeta Patil, Biju K. Raveendran, Sasikumar Punnekkat
MEDIATOR - A Mixed Criticality Deadline Honored Arbiter for Multi-core Real-time Systems. DS-RT (2019)
Geeta Patil, Neethu Bal Mallya, Biju K. Raveendran
MOESIF: a MC/MP cache coherence protocol with improved bandwidth utilisation. Int. J. Embed. Syst. 11 (4) (2019)
Shubhangi K. Gawali, Biju K. Raveendran
DPVFS: a dynamic procrastination cum DVFS scheduler for multi-core hard real-time systems. Int. J. Embed. Syst. 11 (4) (2019)
Mayuri Digalwar, Praveen Gahukar, Biju K. Raveendran, Sudeept Mohan
Energy efficient real-time scheduling algorithm for mixed task set on multi-core processors. Int. J. Embed. Syst. 9 (6) (2017)
Biju K. Raveendran, Pravin Joshi, Sahil Mittal
eduCloud: a VM communication aware, migration efficient cloud for scientific computing. Int. J. Commun. Networks Distributed Syst. 18 (3/4) (2017)
Mayuri Digalwar, Biju K. Raveendran, Sudeept Mohan
LAMCS: A leakage aware DVFS based mixed task set scheduler for multi-core processors. Sustain. Comput. Informatics Syst. 15 (2017)
Kajal Varma, Geeta Patil, Biju K. Raveendran
DTLB: Deterministic TLB for Tightly Bound Hard Real-Time Systems. VLSI Design (2017)
Shubhangi K. Gawali, Biju K. Raveendran
DPS: A dynamic procrastination scheduler for multi-core/multi-processor hard real time systems. CoDIT (2016)
Neethu Bal Mallya, Geeta Patil, Biju K. Raveendran
Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors. VLSI Design (2015)
Neethu Bal Mallya, Geeta Patil, Biju K. Raveendran
Simulation based Performance Study of Cache Coherence Protocols. iNIS (2015)
Biju K. Raveendran, Sundar Balasubramaniam, S. Gurunarayanan
Evaluation of priority based real time scheduling algorithms: choices and tradeoffs. SAC (2008)
Biju K. Raveendran, T. S. B. Sudarshan, Avinash Patil, Komal B. Randive, S. Gurunarayanan
An Energy Efficient Selective Placement Scheme for Set-Associative Data Cache in Embedded System. ESA (2007)
Biju K. Raveendran, Janardan Prasad Misra, Karan Bhatnagar, S. Gurunarayanan
EFFS: Efficient Flash File System for Wireless Sensor Nodes. ESA (2007)
Biju K. Raveendran, K. Durga Prasad, Sundar Balasubramaniam, S. Gurunarayanan
Variants of Priority Scheduling Algorithms for Reducing Context-Switches in Real-Time Systems. ICDCN (2006)
Biju K. Raveendran, Sundar Balasubramaniam, K. Durga Prasad, S. Gurunarayanan
A Context-Switch Reduction Heuristic for Power-Aware Off-Line Scheduling. Asia-Pacific Computer Systems Architecture Conference (2006)