Geeta Patil

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 5

Top Topics

Multiprocessor Architecture

Stochastic Methods

Embedded Processors

Real Time Databases

Top Venues

Int. J. Embed. Syst.

Publications

Arun S. Nair, Geeta Patil, Archit Agarwal, Aboli Vijayan Pai, Biju K. Raveendran, Sasikumar Punnekkat
CAMP: a hierarchical cache architecture for multi-core mixed criticality processors. Int. J. Parallel Emergent Distributed Syst. 39 (3) (2024)
Arun S. Nair, Aboli Vijayan Pai, Biju K. Raveendran, Geeta Patil
MOESIL: A Cache Coherency Protocol for Locked Mixed Criticality L1 Data Cache. DS-RT (2021)
Arun S. Nair, Louella Mesquita Colaco, Geeta Patil, Biju K. Raveendran, Sasikumar Punnekkat
MEDIATOR - A Mixed Criticality Deadline Honored Arbiter for Multi-core Real-time Systems. DS-RT (2019)
Geeta Patil, Neethu Bal Mallya, Biju K. Raveendran
MOESIF: a MC/MP cache coherence protocol with improved bandwidth utilisation. Int. J. Embed. Syst. 11 (4) (2019)
Kajal Varma, Geeta Patil, Biju K. Raveendran
DTLB: Deterministic TLB for Tightly Bound Hard Real-Time Systems. VLSI Design (2017)
Neethu Bal Mallya, Geeta Patil, Biju K. Raveendran
Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors. VLSI Design (2015)
Neethu Bal Mallya, Geeta Patil, Biju K. Raveendran
Simulation based Performance Study of Cache Coherence Protocols. iNIS (2015)