Khawar Sarfraz

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 6

Top Topics

Power Reduction

Write Operations

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Ikramullah Shah, Khawar Sarfraz, Mansun Chan
An Efficient 6TP SRAM-Based CIM Macro With Column ADCs for Binarized Neural Networks. IEEE Trans. Circuits Syst. II Express Briefs 71 (5) (2024)
Danfeng Xu, Yu Kou, Paul Lai, Zichuan Cheng, Tze Yin Cheung, Larry Moser, Yang Zhang, Xiaolong Liu, Man Pio Lam, Haikun Jia, Quan Pan, Wing Hong Szeto, Chi Fai Tang, Ka Fai Mak, Khawar Sarfraz, Tairan Zhu, Ming Kwan, Emily Yim Lee Au, Cormac Conroy, Kai-Keung Chan
8.5 A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm. ISSCC (2021)
Khawar Sarfraz, Mansun Chan
A 1.2V-to-0.4V 3.2GHz-to-14.3MHz Power-Efficient 3-Port Register File in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2017)
Khawar Sarfraz, Jin He, Mansun Chan
A 140-mV Variation-Tolerant Deep Sub-Threshold SRAM in 65-nm CMOS. IEEE J. Solid State Circuits 52 (8) (2017)
Khawar Sarfraz, Mansun Chan
A compact low-power 4-port register file with grounded write bitlines and single-ended read operations. Integr. 55 (2016)
Khawar Sarfraz, Mansun Chan
A voltage-scalable zero-delay-overhead scheme for standby power reduction in dynamic register files. MWSCAS (2016)
Khawar Sarfraz, Mansun Chan
A 65nm 3.2GHz 44.2mW Low-Vt register file with robust low-capacitance dynamic local bitlines. ESSCIRC (2015)
Khawar Sarfraz, Mansun Chan
Nanoscale register file circuit design - Challenges and opportunities. ASICON (2015)
Khawar Sarfraz, Volkan Kursun
Characterization of a low leakage current and high-speed 7T SRAM circuit with wide voltage margins. ISVLSI (2013)
Khawar Sarfraz
A novel low-leakage 8T differential SRAM cell. VLSI-SoC (2011)