8.5 A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm.
Danfeng XuYu KouPaul LaiZichuan ChengTze Yin CheungLarry MoserYang ZhangXiaolong LiuMan Pio LamHaikun JiaQuan PanWing Hong SzetoChi Fai TangKa Fai MakKhawar SarfrazTairan ZhuMing KwanEmily Yim Lee AuCormac ConroyKai-Keung ChanPublished in: ISSCC (2021)