A 140-mV Variation-Tolerant Deep Sub-Threshold SRAM in 65-nm CMOS.
Khawar SarfrazJin HeMansun ChanPublished in: IEEE J. Solid State Circuits (2017)
Keyphrases
- cmos technology
- power consumption
- low power
- nm technology
- random access memory
- low voltage
- leakage current
- silicon on insulator
- high speed
- low cost
- metal oxide semiconductor
- analog vlsi
- power dissipation
- parallel processing
- threshold selection
- power reduction
- embedded dram
- motion vectors
- neural network
- dynamic random access memory
- cmos image sensor
- adaptive threshold
- thresholding method
- circuit design
- deep learning
- data structure
- computer vision