Kazuyoshi Nishimura

Publication Activity (10 Years)

Years Active: 2006-2009
Publications (10 Years): 0

Publications

Jun Terada, Yusuke Ohtomo, Kazuyoshi Nishimura, Hiroaki Katsurai, Shunji Kimura, Naoto Yoshimoto
Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit. ISSCC (2009)
Yusuke Ohtomo, Masafumi Nogawa, Kazuyoshi Nishimura, Shunji Kimura, Tomoaki Yoshida, Tomoaki Kawamura, Minoru Togashi, Kiyomi Kumozaki
A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs. IEICE Trans. Electron. (6) (2008)
Tomoaki Kawamura, Yusuke Ohtomo, Kazuyoshi Nishimura, Noboru Ishihara
A 1ps-Resolution 2ns-Span 10Gb/s Data-Timing Generator with Spectrum Conversion. ISSCC (2008)
Jun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo
A 10.3125Gb/s Burst-Mode CDR Circuit using a δσ DAC. ISSCC (2008)
Yusuke Ohtomo, Hiroshi Koizumi, Kazuyoshi Nishimura, Masafumi Nogawa
A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI. IEICE Trans. Electron. (4) (2008)
Jun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo
A 10.3 Gb/s Burst-Mode CDR Using a ΔΣ DAC. IEEE J. Solid State Circuits 43 (12) (2008)
Takashi Nakanishi, Ken-Ichi Suzuki, Youichi Fukada, Naoto Yoshimoto, Makoto Nakamura, Kazutoshi Kato, Kazuyoshi Nishimura, Yusuke Ohtomo, Makoto Tsubokawa
High sensitivity APD burst-mode receiver for 10Gbit/s TDM-PON system. IEICE Electron. Express 4 (19) (2007)
Masafumi Nogawa, Yusuke Ohtomo, Shunji Kimura, Kazuyoshi Nishimura, Tomoaki Kawamura, Minoru Togashi
A 10Gb/s burst-mode adaptive gain select limiting amplifier in 0.13µm CMOS. ISSCC (2006)
Yusuke Ohtomo, Kazuyoshi Nishimura, Masafumi Nogawa
A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOS. IEEE J. Solid State Circuits 41 (9) (2006)