Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit.
Jun TeradaYusuke OhtomoKazuyoshi NishimuraHiroaki KatsuraiShunji KimuraNaoto YoshimotoPublished in: ISSCC (2009)
Keyphrases
- high speed
- pulse width
- power reduction
- analog circuits
- circuit design
- tunnel diode
- electronic circuits
- analog vlsi
- logic synthesis
- digital circuits
- delay insensitive
- logic circuits
- shift register
- power dissipation
- low power
- power consumption
- cmos technology
- packet loss
- power saving
- vlsi circuits
- chip design
- asynchronous circuits
- neural network
- video data
- quantum computing
- reduction method
- image sequences