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A 10.3125Gb/s Burst-Mode CDR Circuit using a δσ DAC.
Jun Terada
Kazuyoshi Nishimura
Shunji Kimura
Hiroaki Katsurai
Naoto Yoshimoto
Yusuke Ohtomo
Published in:
ISSCC (2008)
Keyphrases
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high speed
digital circuits
analog circuits
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machine learning
image processing
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circuit design
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database
parallel processing
low power
electronic circuits
mixed mode
gallium arsenide