Katarzyna Radecka

Publication Activity (10 Years)

Years Active: 1997-2022
Publications (10 Years): 11

Top Topics

Activity Recognition

Monitoring System

Fusion Algorithm

Top Venues

IEEE J. Biomed. Health Informatics

Publications

Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic
Wearable Vibrotactile System as an Assistive Technology Solution. Mob. Networks Appl. 27 (2) (2022)
Jianing Sun, Katarzyna Radecka, Zeljko Zilic
FoodTracker: A Real-time Food Detection Mobile Application by Deep Convolutional Neural Networks. CoRR (2019)
Jianing Sun, Katarzyna Radecka, Zeljko Zilic
Exploring Better Food Detection via Transfer Learning. MVA (2019)
Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic
A Comprehensive Analysis on Wearable Acceleration Sensors in Human Activity Recognition. Sensors 17 (3) (2017)
Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic
A Novel Algorithm to Reduce Machine Learning Efforts in Real-Time Sensor Data Analysis. MobiHealth (2017)
Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic
Designing and Evaluating a Vibrotactile Language for Sensory Substitution Systems. MobiHealth (2017)
Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic
Respiration Disorders Classification With Informative Features for m-Health Applications. IEEE J. Biomed. Health Informatics 20 (3) (2016)
Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic
Haptic feedback and human performance in a wearable sensor system. BHI (2016)
Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic
Design and Evaluation of an Intelligent Remote Tidal Volume Variability Monitoring System in E-Health Applications. IEEE J. Biomed. Health Informatics 19 (5) (2015)
Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic
Movement analysis of the chest compartments and a real-time quality feedback during breathing therapy. Netw. Model. Anal. Health Informatics Bioinform. 4 (1) (2015)
Yu Pang, Yafeng Yan, Jinzhao Lin, Guoquan Li, Huawei Huang, Lei Shi, Katarzyna Radecka
ICAT: Engine to Perform Range Analysis and Allocate Bit-Widths for Arithmetic Datapaths. J. Circuits Syst. Comput. 24 (2) (2015)
Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic
Multi-sensor blind recalibration in mHealth applications. IHTC (2014)
Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic
Affordable erehabilitation monitoring platform. IHTC (2014)
Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic
A Medical Cloud-Based Platform for Respiration Rate Measurement and Hierarchical Classification of Breath Disorders. Sensors 14 (6) (2014)
Omid Sarbishei, Katarzyna Radecka, Zeljko Zilic
A hybrid arithmetic transform for precision analysis of floating-point polynomial specifications. NEWCAS (2014)
Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic
Automated diagnosis of knee pathology using sensory data. MobiHealth (2014)
Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic
Development of a Remote Monitoring System for Respiratory Analysis. IoT360 (1) (2014)
Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic
Design of an e-Health Respiration and Body Posture Monitoring System and Its Application for Rib Cage and Abdomen Synchrony Analysis. BIBE (2014)
Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic
Tidal volume variability and respiration rate estimation using a wearable accelerometer sensor. MobiHealth (2014)
Omid Sarbishei, Benjamin Nahill, Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic, Boris Karajica
An efficient fault-tolerant sensor fusion algorithm for accelerometers. BSN (2013)
Yu Pang, Qian Lei, Jinzhao Lin, Zhiyong Luo, Zhangyong Li, Zeljko Zilic, Katarzyna Radecka
SAR Computation and Channel Modeling of Body Area Network. BODYNETS (2013)
Omid Sarbishei, Atena Roshan Fekr, Majid Janidarmian, Benjamin Nahill, Katarzyna Radecka
A minimum MSE sensor fusion algorithm with tolerance to multiple faults. ETS (2013)
Sayeeda Sultana, Katarzyna Radecka
Testing reversible adder/subtractor for missing control points. MWSCAS (2013)
Omid Sarbishei, Katarzyna Radecka
On the Fixed-Point Accuracy Analysis and Optimization of Polynomial Specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (6) (2013)
Sayeeda Sultana, Atena Roshan Fekr, Katarzyna Radecka
SAT-based reversible gate/wire replacement fault testing. MWSCAS (2013)
Atena Roshan Fekr, Majid Janidarmian, Omid Sarbishei, Benjamin Nahill, Katarzyna Radecka, Zeljko Zilic
MSE minimization and fault-tolerant data fusion for multi-sensor systems. ICCD (2012)
Majid Janidarmian, Zeljko Zilic, Katarzyna Radecka
Issues in Multi-valued Multi-modal Sensor Fusion. ISMVL (2012)
Omid Sarbishei, Katarzyna Radecka, Zeljko Zilic
Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (3) (2012)
Omid Sarbishei, Katarzyna Radecka
Fixed-point accuracy analysis of datapaths with mixed CORDIC and polynomial computations. ASP-DAC (2012)
Omid Sarbishei, Katarzyna Radecka
Verification of fixed-point datapaths with comparator units using Constrained Arithmetic Transform (CAT). ISCAS (2012)
Omid Sarbishei, Katarzyna Radecka
On the Fixed-Point Accuracy Analysis and Optimization of FFT Units with CORDIC Multipliers. IEEE Symposium on Computer Arithmetic (2011)
Zeljko Zilic, Katarzyna Radecka
Fault tolerant glucose sensor readout and recalibration. Wireless Health (2011)
Yu Pang, Shaoquan Wang, Zhilong He, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka
Positive Davio-based synthesis algorithm for reversible logic. ICCD (2011)
Omid Sarbishei, Katarzyna Radecka
Analysis of Mean-Square-Error (MSE) for fixed-point FFT units. ISCAS (2011)
Yu Pang, Katarzyna Radecka
An efficient algorithm of performing range analysis for fixed-point arithmetic circuits based on SAT checking. ISCAS (2011)
Sayeeda Sultana, Katarzyna Radecka
Rev-Map: A Direct Gateway from Classical Irreversible Network to Reversible Network. ISMVL (2011)
Yu Pang, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka
A novel method of synthesizing reversible logic. ISCAS (2011)
Sayeeda Sultana, Katarzyna Radecka
Reversible implementation of square-root circuit. ICECS (2011)
Sayeeda Sultana, Katarzyna Radecka, Yu Pang
A study on relating redundancy removal in classical circuits to reversible mapping. ICCD (2011)
Yu Pang, Katarzyna Radecka, Zeljko Zilic
An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits. ASP-DAC (2011)
Yu Pang, Katarzyna Radecka, Zeljko Zilic
An efficient method to perform range analysis for DSP circuits. ICECS (2010)
Omid Sarbishei, Yu Pang, Katarzyna Radecka
Analysis of range and precision for fixed-point linear arithmetic circuits with feedbacks. HLDVT (2010)
Omid Sarbishei, Katarzyna Radecka
Analysis of precision for scaling the intermediate variables in fixed-point arithmetic circuits. ICCAD (2010)
Yu Pang, Katarzyna Radecka, Zeljko Zilic
Optimization of Imprecise Circuits Represented by Taylor Series and Real-Valued Polynomials. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (8) (2010)
Sayeeda Sultana, Shahriar Al-Imam, Katarzyna Radecka
Design for Testability of QCA Logic Under Stuck-at-value Fault Model. J. Multiple Valued Log. Soft Comput. 14 (1-2) (2008)
Yu Pang, Katarzyna Radecka
Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transform. DAC (2008)
Ali Khazamipour, Katarzyna Radecka
Adiabatic Implementation of Reversible Logic Circuits in CMOS Technology. J. Multiple Valued Log. Soft Comput. 13 (1-2) (2007)
Zeljko Zilic, Katarzyna Radecka
Scaling and Better Approximating Quantum Fourier Transform by Higher Radices. IEEE Trans. Computers 56 (2) (2007)
Zeljko Zilic, Katarzyna Radecka, Ali Kazamiphur
Reversible circuit technology mapping from non-reversible specifications. DATE (2007)
Rong Zhang, Zeljko Zilic, Katarzyna Radecka
Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes. VTS (2006)
Yu Pang, Katarzyna Radecka, Zeljko Zilic
Algorithms for Compositions of Arithmetic Transforms and Their Extensions. ICECS (2006)
Yu Pang, Katarzyna Radecka, Zeljko Zilic
Arithmetic Transforms of Imprecise Datapaths by Taylor Series Conversion. ICECS (2006)
Sayeeda Sultana, Shahriar Al-Imam, Katarzyna Radecka
Testing QCA Modular Logic. ICECS (2006)
Katarzyna Radecka, Zeljko Zilic
Design Verification by Test Vectors and Arithmetic Transform Universal Test Set. IEEE Trans. Computers 53 (5) (2004)
Man Wah Chiang, Zeljko Zilic, Jean-Samuel Chenard, Katarzyna Radecka
Architectures of Increased Availability Wireless Sensor Network Nodes. ITC (2004)
Ahmed Usman Khalid, Zeljko Zilic, Katarzyna Radecka
FPGA Emulation of Quantum Circuits. ICCD (2004)
Katarzyna Radecka, Zeljko Zilic
Identifying Redundant Wire Replacements for Synthesis and Verification. VLSI Design (2002)
Katarzyna Radecka, Zeljko Zilic
Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms. ICCAD (2002)
Zeljko Zilic, Katarzyna Radecka
The Role of Super-Fast Transforms in Speeding Up Quantum Computations. ISMVL (2002)
Zeljko Zilic, Katarzyna Radecka
: Identifying redundant gate replacements in verification by error modeling. ITC (2001)
Katarzyna Radecka, Zeljko Zilic
Arithmetic Transforms for Verifying Compositions of Sequential Datapaths. ICCD (2001)
Katarzyna Radecka, Zeljko Zilic, Karim Khordoc
Combinational verification by simulations, SAT and BDDs. ICECS (2001)
Katarzyna Radecka, Zeljko Zilic
Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling. VTS (2000)
Zeljko Zilic, Katarzyna Radecka
On Feasible Multivariate Polynomial Interpolations over Arbitrary Fields. ISSAC (1999)
Katarzyna Radecka, Janusz Rajski, Jerzy Tyszer
Arithmetic built-in self-test for DSP cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (11) (1997)