Combinational verification by simulations, SAT and BDDs.
Katarzyna RadeckaZeljko ZilicKarim KhordocPublished in: ICECS (2001)
Keyphrases
- asynchronous circuits
- pseudo boolean constraints
- model checking
- sat solvers
- heuristic search
- search strategies
- timed automata
- sat solving
- satisfiability problem
- binary decision diagrams
- formal methods
- sat problem
- signature verification
- propositional satisfiability
- face verification
- simulation model
- numerical simulations
- evolutionary algorithm
- formal verification
- boolean satisfiability
- phase transition
- variable ordering
- state space