Sayeeda Sultana

Publication Activity (10 Years)

Years Active: 2006-2013
Publications (10 Years): 0

Top Topics

Transformation Matrix

Boolean Satisfiability

Top Venues

Publications

Sayeeda Sultana, Katarzyna Radecka
Testing reversible adder/subtractor for missing control points. MWSCAS (2013)
Sayeeda Sultana, Atena Roshan Fekr, Katarzyna Radecka
SAT-based reversible gate/wire replacement fault testing. MWSCAS (2013)
Yu Pang, Shaoquan Wang, Zhilong He, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka
Positive Davio-based synthesis algorithm for reversible logic. ICCD (2011)
Sayeeda Sultana, Katarzyna Radecka
Rev-Map: A Direct Gateway from Classical Irreversible Network to Reversible Network. ISMVL (2011)
Yu Pang, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka
A novel method of synthesizing reversible logic. ISCAS (2011)
Sayeeda Sultana, Katarzyna Radecka
Reversible implementation of square-root circuit. ICECS (2011)
Sayeeda Sultana, Katarzyna Radecka, Yu Pang
A study on relating redundancy removal in classical circuits to reversible mapping. ICCD (2011)
Sayeeda Sultana, Shahriar Al-Imam, Katarzyna Radecka
Design for Testability of QCA Logic Under Stuck-at-value Fault Model. J. Multiple Valued Log. Soft Comput. 14 (1-2) (2008)
Sayeeda Sultana, Shahriar Al-Imam, Katarzyna Radecka
Testing QCA Modular Logic. ICECS (2006)