Jun Ho Bahn

Publication Activity (10 Years)

Years Active: 2007-2012
Publications (10 Years): 0

Top Topics

Distributed Video Coding

Network On Chip

Single Processor

Top Venues

IET Comput. Digit. Tech.

Publications

W.-H. Hu, C.-Y. Chen, Jun Ho Bahn, Nader Bagherzadeh
Parallel low-density parity check decoding on a network-on-chip-based multiprocessor platform. IET Comput. Digit. Tech. 6 (2) (2012)
Yoon Seok Yang, Jun Ho Bahn, Seung Eun Lee, Jungsook Yang, Nader Bagherzadeh
Parallel processing for block ciphers on a fault tolerant networked processor array. Int. J. High Perform. Syst. Archit. 2 (3/4) (2010)
Wen-Hsiang Hu, Jun Ho Bahn, Nader Bagherzadeh
Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform. SBAC-PAD (2009)
Yoon Seok Yang, Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh
Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip. ITNG (2009)
Jun Ho Bahn, Jungsook Yang, Wen-Hsiang Hu, Nader Bagherzadeh
Parallel FFT Algorithms on Network-on-Chips. J. Circuits Syst. Comput. 18 (2) (2009)
Wolfgang Trumler, Sebastian Schlingmann, Theo Ungerer, Jun Ho Bahn, Nader Bagherzadeh
Self-optimized Routing in a Network on-a-Chip. BICC (2008)
Jun Ho Bahn, Jungsook Yang, Nader Bagherzadeh
Parallel FFT Algorithms on Network-on-Chips. ITNG (2008)
Jun Ho Bahn, Nader Bagherzadeh
Design of simulation and analytical models for a 2D-meshed asymmetric adaptive router. IET Comput. Digit. Tech. 2 (1) (2008)
Seung Eun Lee, Jun Ho Bahn, Yoon Seok Yang, Nader Bagherzadeh
A Generic Network Interface Architecture for a Networked Processor Array (NePA). ARCS (2008)
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungsook Yang, Nader Bagherzadeh
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture. Parallel Process. Lett. 18 (2) (2008)
Jun Ho Bahn, Nader Bagherzadeh
Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip (NoC) Architecture. CSICC (2008)
Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh
On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture. ITNG (2007)
Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh
Design of a router for network-on-chip. Int. J. High Perform. Syst. Archit. 1 (2) (2007)
Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP). SBAC-PAD (2007)