Parallel low-density parity check decoding on a network-on-chip-based multiprocessor platform.
W.-H. HuC.-Y. ChenJun Ho BahnNader BagherzadehPublished in: IET Comput. Digit. Tech. (2012)
Keyphrases
- low density parity check
- ldpc codes
- decoding algorithm
- multi processor
- network on chip
- single processor
- distributed memory
- message passing
- shared memory
- error correction
- channel coding
- distributed video coding
- interconnection networks
- parallel architectures
- parallel processors
- low complexity
- real time
- routing algorithm
- parallel programming
- parallel implementation
- image transmission
- network simulator
- multi core processors
- parallel computing
- error resilience
- rate allocation
- unequal error protection
- turbo codes
- belief propagation
- distributed systems
- high speed
- computational complexity