Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip (NoC) Architecture.
Jun Ho BahnNader BagherzadehPublished in: CSICC (2008)
Keyphrases
- network on chip
- multi processor
- packet switched
- routing algorithm
- single processor
- shared memory
- program execution
- network simulator
- interconnection networks
- multi core processors
- parallel architectures
- parallel architecture
- power dissipation
- distributed memory
- data transfer
- ad hoc networks
- parallel processing
- multistage
- data management
- low cost
- network management