José Luís Güntzel

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 32

Top Topics

Hardware Architectures

Motion Estimation

Top Venues

Publications

Tiago Augusto Fontana, Erfan Aghaeekiasaraee, Renan Netto, Sheiny Fabre Almeida, Upma Gandhi, Laleh Behjat, José Luís Güntzel
ILPGRC: ILP-Based Global Routing Optimization With Cell Movements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (1) (2024)
André Beims Bräscher, Gabriela Furtado Da Silveira, Luiz Henrique Cancellier, Ismael Seidel, Mateus Grellert, José Luís Güntzel
A New Approach to Video Coding Leveraging Hybrid Coding and Video Frame Interpolation. SBCCI (2023)
Vanio Rodrigues Filho, Ismael Seidel, Nicole Citadin, Marcio Monteiro, Mateus Grellert, José Luís Güntzel
Low-Energy and Reduced-Area Hardware Architecture for the Versatile Video Coding FME. SBCCI (2023)
Erfan Aghaeekiasaraee, Aysa Fakheri Tabrizi, Tiago Augusto Fontana, Renan Netto, Sheiny Fabre Almeida, Upma Gandhi, José Luís Güntzel, David T. Westwick, Laleh Behjat
CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes. ACM Trans. Design Autom. Electr. Syst. 28 (5) (2023)
Renan Netto, Sheiny Fabre, Tiago Augusto Fontana, Vinicius S. Livramento, Laércio Lima Pilla, Laleh Behjat, José Luís Güntzel
Algorithm Selection Framework for Legalization Using Deep Convolutional Neural Networks and Transfer Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (5) (2022)
Sheiny Fabre Almeida, Aysa Fakheri Tabrizi, Erfan Aghaeekiasaraee, Renan Netto, Tiago Augusto Fontana, Upma Gandh, José Luís Güntzel, Laleh Behjat, Cristina Meinhardt
E-RVP: An Initial Design Rule Violation Predictor Using Placement Information. ICECS 2022 (2022)
Marcio Monteiro, Ismael Seidel, Mateus Grellert, José Luís Güntzel, Leonardo Bandeira Soares, Cristina Meinhardt
Exploring the Impacts of Multiple Kernel Sizes of Gaussian Filters Combined to Approximate Computing in Canny Edge Detection. LASCAS (2022)
Sheiny Fabre Almeida, José Luís Güntzel, Laleh Behjat, Cristina Meinhardt
Routability-Driven Detailed Placement Using Reinforcement Learning. VLSI-SoC (2022)
Luiz Henrique Cancellier, Mateus Grellert, José Luís Güntzel, Luís Alberto da Silva Cruz
Autoencoder Model Exploration for Multi-Layer Video Compression. EUVIP (2022)
Tiago Augusto Fontana, Erfan Aghaeekiasaraee, Renan Netto, Sheiny Fabre Almeida, Upma Gandh, Aysa Fakheri Tabrizi, David T. Westwick, Laleh Behjat, José Luís Güntzel
ILP-Based Global Routing Optimization with Cell Movements. ISVLSI (2021)
Marcio Monteiro, Pedro Aquino Silva, Ismael Seidel, Mateus Grellert, Leonardo Bandeira Soares, José Luís Güntzel, Cristina Meinhardt
Design of Energy-Efficient Gaussian Filters by Combining Refactoring and Approximate Adders. ISCAS (2021)
Ismael Seidel, Vanio Rodrigues Filho, Mateus Grellert, Luciano Volcan Agostini, José Luís Güntzel
SAD or SATD? How the Distortion Metric Impacts a Fractional Motion Estimation VLSI Architecture. MMSP (2021)
Vanio Rodrigues Filho, Marcio Monteiro, Ismael Seidel, Mateus Grellert, José Luís Güntzel
Hardware-Friendly Search Patterns for the Versatile Video Coding Fractional Motion Estimation. MMSP (2021)
Gabriel B. Sant'Anna, Luiz Henrique Cancellier, Ismael Seidel, Mateus Grellert, José Luís Güntzel
Relying on a Rate Constraint to Reduce Motion Estimation Complexity. ICASSP (2021)
Vanio Rodrigues Filho, Marcio Monteiro, Ismael Seidel, Mateus Grellert, José Luís Güntzel
Standalone Rate-Distortion FME Architecture. SBCCI (2020)
Michael Hübner, José Luís Güntzel
Guest Editors' Introduction: SBCCI 2018. IEEE Des. Test 37 (3) (2020)
Ismael Seidel, Marcio Monteiro, Bruno Bonotto, Luciano Volcan Agostini, José Luís Güntzel
Energy-Efficient Hadamard-Based SATD Hardware Architectures Through Calculation Reuse. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2019)
Renan Netto, Sheiny Fabre, Tiago Augusto Fontana, Vinicius S. Livramento, Laércio Lima Pilla, José Luís Güntzel
How Deep Learning Can Drive Physical Synthesis Towards More Predictable Legalization. ISPD (2019)
Douglas Lohmann, Alexis Huf, Djones Lettnin, Frank Siqueira, José Luís Güntzel
A Domain-specific Language for Automated Fault Injection in SystemC Models. ICECS (2018)
Marcio Monteiro, Ismael Seidel, José Luís Güntzel
On the calculation reuse in hadamard-based SATD. LASCAS (2018)
Ismael Seidel, Vanio Rodrigues Filho, Luciano Volcan Agostini, José Luís Güntzel
Coding- and Energy-Efficient FME Hardware Design. ISCAS (2018)
Luiz Henrique Cancellier, Ismael Seidel, José Luís Güntzel
On HEVC Robustness to Integer Motion Estimation Pruning. ICECS (2018)
Sheiny Fabre, José Luís Güntzel, Laércio Lima Pilla, Renan Netto, Tiago Fontana, Vinicius S. Livramento
Enhancing Multi-Threaded Legalization Through k-d Tree Circuit Partitioning. SBCCI (2018)
Tiago Augusto Fontana, Sheiny Almeida, Renan Netto, Vinicius S. Livramento, Chrystian Guth, Laércio Lima Pilla, José Luís Güntzel
Exploiting cache locality to speedup register clustering. SBCCI (2017)
Tiago Fontana, Renan Netto, Vinicius S. Livramento, Chrystian Guth, Sheiny Almeida, Laércio Lima Pilla, José Luís Güntzel
How Game Engines Can Inspire EDA Tools Development: A use case for an open-source physical design library. ISPD (2017)
André Beims Bräscher, Ismael Seidel, José Luís Güntzel
Improving the energy efficiency of a low-area SATD hardware architecture using fine grain PDE. SBCCI (2017)
Luiz Henrique Cancellier, Ismael Seidel, José Luís Güntzel
Block matching hardware architecture for SATD-based successive elimination. SBCCI (2017)
Renan Netto, Chrystian Guth, Vinicius S. Livramento, Márcio Castro, Laércio Lima Pilla, José Luís Güntzel
Exploiting parallelism to speed up circuit legalization. ICECS (2016)
Ismael Seidel, José Luís Güntzel, Luciano Volcan Agostini
Coarse grain partial distortion elimination for Hadamard ME in HEVC. ICECS (2016)
Vinicius S. Livramento, Renan Netto, Chrystian Guth, José Luís Güntzel, Luiz Cláudio Villar dos Santos
Clock-Tree-Aware Incremental Timing-Driven Placement. ACM Trans. Design Autom. Electr. Syst. 21 (3) (2016)
Renan Netto, Vinicius S. Livramento, Chrystian Guth, Luiz C. V. dos Santos, José Luís Güntzel
Evaluating the impact of circuit legalization on incremental optimization techniques. SBCCI (2016)
Renan Netto, Vinicius S. Livramento, Chrystian Guth, Luiz C. V. dos Santos, José Luís Güntzel
Speeding up Incremental Legalization with Fast Queries to Multidimensional Trees. ISVLSI (2016)
Ismael Seidel, André Beims Bräscher, José Luís Güntzel
Combining Pel Decimation with Partial Distortion Elimination to increase SAD energy efficiency. PATMOS (2015)
Chrystian Guth, Vinicius S. Livramento, Renan Netto, Renan Fonseca, José Luís Güntzel, Luiz C. V. dos Santos
Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression. ISPD (2015)
Luiz Henrique Cancellier, André Beims Bräscher, Ismael Seidel, José Luís Güntzel
Energy-Efficient Hadamard-Based SATD Architectures. SBCCI (2014)
Vinicius S. Livramento, Chrystian Guth, José Luís Güntzel, Marcelo O. Johann
Fast and efficient lagrangian relaxation-based discrete gate sizing. DATE (2013)
Ismael Seidel, Bruno George de Moraes, André Beims Bräscher, José Luís Güntzel
On the impacts of pel decimation and High-Vt/Low-Vdd on SAD calculation. SBCCI (2013)
Edson Sorato, Renan Netto, Pedro Michel, José Luís Güntzel, Adalbery R. Castro, Aldebaro Klautau
VLSI architectures for Digital Modulation Classification using Support Vector Machines. LASCAS (2013)
Ismael Seidel, Bruno George de Moraes, José Luís Güntzel
A low-power configurable VLSI architecture for sum of absolute differences calculation. LASCAS (2013)
Vinicius dos S. Livramento, Chrystian Guth, José Luís Güntzel, Marcelo O. Johann
Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimization. ICECS (2012)
Vinicius S. Livramento, Bruno George de Moraes, Brunno Abner Machado, José Luís Güntzel
An energy-efficient 8×8 2-D DCT VLSI architecture for battery-powered portable devices. ISCAS (2011)
Jucemar Monteiro, José Luís Güntzel, Luciano Volcan Agostini
A1CSA: An energy-efficient fast adder architecture for cell-based VLSI design. ICECS (2011)
Eduardo Mesquita, Helen Franck, Luciano Volcan Agostini, José Luís Güntzel
RIC Fast Adder and its Set Tolerant Implementation in FPGAs. FPL (2007)
Luciano Volcan Agostini, Roger Endrigo Carvalho Porto, José Luís Güntzel, Ivan Saraiva Silva, Sergio Bampi
High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard. ISCAS (2006)
Luciano Volcan Agostini, Roger Endrigo Carvalho Porto, Sergio Bampi, Leandro Rosa, José Luís Güntzel, Ivan Saraiva Silva
High throughput architecture for H.264/AVC forward transforms block. ACM Great Lakes Symposium on VLSI (2006)
Cristiano Santos, Daniel Lima Ferrão, Ricardo Reis, José Luís Güntzel
Incremental timing optimization for automatic layout generation. ISCAS (4) (2005)
Cristiano Lazzari, Cristiano Viana Domingues, José Luís Güntzel, Ricardo Reis
A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits. VLSI-SoC (Selected Papers) (2003)
Gustavo Wilke, José Luís Güntzel, Márcio Bystronski, Ana Cristina M. Pinto, Ricardo Reis
Finding the Critical Delay of Combinational Blocks by Floating Vector Simulation and Path Tracing. SBCCI (2002)
José Luís Güntzel, Gustavo Wilke, Márcio Bystronski, Ana Cristina Medina Pinto, Ricardo Reis
A Comparison Between Testability Measures Applied to Complex Gates. LATW (2002)
José Luís Güntzel, Ana Cristina Medina Pinto, Ricardo Reis
A Timed Calculus for ATG-Based Timing Analysis with Complex Gates. LATW (2001)
José Luís Güntzel, A. C. Medina Pinto, Eduardo D'Avila, Ricardo Reis
ATG-Based Timing Analysis of Circuits Containing Complex Gates. SBCCI (2000)
José Luís Güntzel, A. C. Medina Pinto, Fernando Moraes, Ricardo Reis
An Improved Path Enumeration Method Considering Different Fall and Rise Gate Delays. SBCCI (1998)