Block matching hardware architecture for SATD-based successive elimination.
Luiz Henrique CancellierIsmael SeidelJosé Luís GüntzelPublished in: SBCCI (2017)
Keyphrases
- block matching motion estimation
- hardware architecture
- successive elimination
- successive elimination algorithm
- block matching
- motion estimation
- video compression
- hardware implementation
- motion compensation
- video coding
- motion vectors
- optical flow
- efficient implementation
- field programmable gate array
- associative memory
- motion field
- low complexity
- video sequences
- spatial domain
- inter frame
- computational complexity
- early termination
- machine learning
- motion model
- reference frame
- dynamic programming
- high quality
- image sequences
- computer vision