Low-Energy and Reduced-Area Hardware Architecture for the Versatile Video Coding FME.
Vanio Rodrigues FilhoIsmael SeidelNicole CitadinMarcio MonteiroMateus GrellertJosé Luís GüntzelPublished in: SBCCI (2023)
Keyphrases
- low energy
- video coding
- hardware architecture
- block matching motion estimation
- motion estimation
- electron microscopy
- motion compensated
- hardware implementation
- rate distortion
- motion compensation
- video compression
- bit rate
- motion vectors
- video codec
- efficient implementation
- protein folding
- macroblock
- field programmable gate array
- coarse grained
- associative memory
- neural network
- image processing
- signal processing
- computational complexity
- pattern recognition
- high quality