Joakim Urdahl

Publication Activity (10 Years)

Years Active: 2010-2020
Publications (10 Years): 6

Top Venues

MBMV

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

FDL

PATMOS

Kaiserslautern University of Technology, Germany (PHD)

Education History

Kaiserslautern University of Technology, Germany

PHD

Publications

Tobias Ludwig, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
Properties First - Correct-By-Construction RTL Design in System-Level Design Flows. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Shrinidhi Udupi, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
Exploiting Hardware Unobservability for Low-Power Design and Safety Analysis in Formal Verification-Driven Design Flows. IEEE Trans. Very Large Scale Integr. Syst. 27 (6) (2019)
Mohammad Rahmani Fadiheh, Joakim Urdahl, Srinivasa Shashank Nuthakki, Subhasish Mitra, Clark W. Barrett, Dominik Stoffel, Wolfgang Kunz
Symbolic quick error detection using symbolic initial state for pre-silicon verification. DATE (2018)
Shrinidhi Udupi, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
Dynamic Power Optimization Based on Formal Property Checking of Operations. VLSI Design (2017)
Shrinidhi Udupi, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
Dynamic Power Optimization based on Formal Property Checking of Operations. MBMV (2017)
Joakim Urdahl, Shrinidhi Udupi, Tobias Ludwig, Dominik Stoffel, Wolfgang Kunz
Properties first? a new design methodology for hardware, and its perspectives in safety analysis. ICCAD (2016)
Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
Architectural system modeling for correct-by-construction RTL design. FDL (2015)
Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
Architectural System Modeling for Correct-by-Construction RTL Design. MBMV (2015)
Wolfgang Kunz, Dominik Stoffel, Joakim Urdahl
T4B: Formal verification in system-on-chip design: Scientific foundations and practical methodology. SoCC (2014)
Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
Path Predicate Abstraction for Sound System-Level Models of RT-Level Circuit Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (2) (2014)
Joakim Urdahl, Shrinidhi Udupi, Dominik Stoffel, Wolfgang Kunz
Formal system-on-chip verification: An operation-based methodology and its perspectives in low power design. PATMOS (2013)
Joakim Urdahl, Dominik Stoffel, Markus Wedler, Wolfgang Kunz
System verification of concurrent RTL modules by compositional path predicate abstraction. DAC (2012)
Joakim Urdahl, Dominik Stoffel, Jörg Bormann, Markus Wedler, Wolfgang Kunz
Path predicate abstraction by complete interval property checking. FMCAD (2010)

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Publication Activity (10 Years)

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Joakim Urdahl