Formal system-on-chip verification: An operation-based methodology and its perspectives in low power design.
Joakim UrdahlShrinidhi UdupiDominik StoffelWolfgang KunzPublished in: PATMOS (2013)
Keyphrases
- low power
- power consumption
- single chip
- design methodology
- high speed
- low power consumption
- low cost
- logic circuits
- cmos technology
- power dissipation
- vlsi architecture
- digital signal processing
- gate array
- wireless transmission
- formal methods
- hardware and software
- nm technology
- ultra low power
- embedded systems
- mixed signal
- model checking
- vlsi circuits
- design process
- real time
- design considerations
- formal specification
- high power
- power reduction
- image processing