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Exploiting Hardware Unobservability for Low-Power Design and Safety Analysis in Formal Verification-Driven Design Flows.
Shrinidhi Udupi
Joakim Urdahl
Dominik Stoffel
Wolfgang Kunz
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2019)
Keyphrases
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low power
formal verification
single chip
low cost
power consumption
circuit design
design process
digital signal processing
logic circuits
vlsi architecture
real time