Jian Zhang

Publication Activity (10 Years)

Years Active: 2012-2016
Publications (10 Years): 2

Top Topics

Cmos Technology

Positive Or Negative

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Jian Zhang, Giovanni De Micheli, Ernesto Sánchez, Matteo Sonza Reorda
A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors. ACM J. Emerg. Technol. Comput. Syst. 13 (2) (2016)
Jian Zhang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
A surface potential and current model for polarity-controllable silicon nanowire FETs. ESSDERC (2015)
Xifan Tang, Jian Zhang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs. ISCAS (2014)
Jian Zhang, Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2014)
Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Jian Zhang, Giovanni De Micheli
Advanced system on a chip design based on controllable-polarity FETs. DATE (2014)
Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Jian Zhang, Giovanni De Micheli
Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors. IEEE Trans. Circuits Syst. II Express Briefs (10) (2013)
Jian Zhang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs. ISCAS (2013)
Shashikanth Bobba, Pierre-Emmanuel Gaillardon, Jian Zhang, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli
Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors. NANOARCH (2012)