Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors.
Shashikanth BobbaPierre-Emmanuel GaillardonJian ZhangMichele De MarchiDavide SacchettoYusuf LeblebiciGiovanni De MicheliPublished in: NANOARCH (2012)
Keyphrases
- cmos technology
- design process
- metal oxide semiconductor
- optimization process
- low power
- circuit design
- conceptual model
- field effect transistors
- optimization algorithm
- integrated circuit
- chip design
- neural network
- optimal design
- design tools
- micron cmos
- simultaneous optimization
- design processes
- high density
- low cost
- software engineering