Hideki Asai

Publication Activity (10 Years)

Years Active: 1985-2022
Publications (10 Years): 15

Top Topics

Top Venues

Publications

S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai
Accelerating Symmetric Rank-1 Quasi-Newton Method with Nesterov's Gradient for Training Neural Networks. Algorithms 15 (1) (2022)
S. Indrapriyadarsini, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai
On the Practical Robustness of the Nesterov's Accelerated Quasi-Newton Method. AAAI (2022)
S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai
A Stochastic Momentum Accelerated Quasi-Newton Method for Neural Networks (Student Abstract). AAAI (2022)
S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai
A modified limited memory Nesterov's accelerated quasi-Newton. CoRR (2021)
S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai
A Neural Network Approach to Analog Circuit Design Optimization using Nesterov's Accelerated Quasi-Newton Method. ISCAS (2020)
S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai
A Nesterov's Accelerated quasi-Newton method for Global Routing using Deep Reinforcement Learning. CoRR (2020)
S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Hideki Asai
A Stochastic Quasi-Newton Method with Nesterov's Accelerated Gradient. ECML/PKDD (1) (2019)
Sota Yasuda, Shahrzad Mahboubi, S. Indrapriyadarsini, Hiroshi Ninomiya, Hideki Asai
A Stochastic Variance Reduced Nesterov's Accelerated Quasi-Newton Method. CoRR (2019)
Sota Yasuda, Shahrzad Mahboubi, S. Indrapriyadarsini, Hiroshi Ninomiya, Hideki Asai
A Stochastic Variance Reduced Nesterov's Accelerated Quasi-Newton Method. ICMLA (2019)
Shahrzad Mahboubi, S. Indrapriyadarsini, Hiroshi Ninomiya, Hideki Asai
Momentum Acceleration of Quasi-Newton Training for Neural Networks. PRICAI (2) (2019)
S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Hideki Asai
A Stochastic Quasi-Newton Method with Nesterov's Accelerated Gradient. CoRR (2019)
S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Hideki Asai
An Adaptive Stochastic Nesterov Accelerated Quasi Newton Method for Training RNNs. CoRR (2019)
S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Hideki Asai
Implementation of a modified Nesterov's Accelerated quasi-Newton Method on Tensorflow. CoRR (2019)
S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Hideki Asai
Implementation of a Modified Nesterov's Accelerated Quasi-Newton Method on Tensorflow. ICMLA (2018)
Hideki Asai
SI/PI/EMI simulation techniques and application to automotive electronic design issues. MIXDES (2017)
Takahiro Takasaki, Tadatoshi Sekine, Hideki Asai
HIE-block latency insertion method for fast transient simulation of nonuniform multiconductor transmission lines. ASP-DAC (2014)
Hideki Asai
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2014)
Tadatoshi Sekine, Hideki Asai
Unconditionally stable explicit method for the fast 3-D simulation of on-chip power distribution network with through silicon via. ASP-DAC (2013)
Hiroki Kurobe, Tadatoshi Sekine, Hideki Asai
Predictor-corrector latency insertion method for fast transient analysis of ill-constructed circuits. ASP-DAC (2012)
Shuichi Aono, Masaki Unno, Hideki Asai
A novel FDTD algorithm based on alternating-direction explicit method with PML absorbing boundary condition. ASP-DAC (2010)
Yuji Okazaki, Takanori Uno, Hideki Asai
An Optimization System with Parallel Processing for Reducing Common-Mode Current on Electronic Control Unit. IEICE Trans. Electron. (6) (2010)
Takanori Uno, Kouji Ichikawa, Yuichi Mabuchi, Atsushi Nakamura, Yuji Okazaki, Hideki Asai
An Approach for Practical Use of Common-Mode Noise Reduction Technique for In-Vehicle Electronic Equipment. IEICE Trans. Commun. (7) (2010)
Takayuki Watanabe, Hideki Asai
Equivalent circuit modeling of multilayered power/ground planes for fast transient simulation. DATE (2010)
Tadatoshi Sekine, Hideki Asai
CMOS Circuit Simulation Using Latency Insertion Method. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2009)
Yuichi Tanji, Hideki Asai, Masayoshi Oda, Yoshifumi Nishio, Akio Ushida
Fast Simulation Technique of Plane Circuits via Two-Layer CNN-Based Modeling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Yuichi Tanji, Takayuki Watanabe, Hideki Asai
Generating stable and sparse reluctance/inductance matrix under insufficient conditions. ASP-DAC (2008)
Yuya Nakazono, Hideki Asai
Acceleration of ADI-FDTD Method by Gauss-Seidel Relaxation Approach. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2008)
Tadatoshi Sekine, Yuichi Tanji, Hideki Asai
Matrix Order Reduction by Nodal Analysis Formulation and Relaxation-Based Fast Simulation for Power/Ground Plane. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2008)
Akira Tsuzaki, Toshio Unno, Yuichi Tanji, Hideki Asai
A fast transient simulation based on Model Order Reduction and RLCG-MNA formulation. ECCTD (2007)
Takayuki Watanabe, Yuichi Tanji, Hidemasa Kubota, Hideki Asai
Fast Transient Simulation of Power Distribution Networks Containing Dispersion Based on Parallel-Distributed Leapfrog Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2007)
Yuya Nakazono, Hideki Asai
Application of Relaxation-Based Technique to ADI-FDTD Method and Its Estimation. ISCAS (2007)
Hiroshi Ninomiya, Kimihiko Numayama, Hideki Asai
Two-staged Tabu Search for Floorplan Problem Using O-Tree Representation. IEEE Congress on Evolutionary Computation (2006)
Hidemasa Kubota, Yuichi Tanji, Takayuki Watanabe, Hideki Asai
An Enhanced Time-Domain Circuit Simulation Technique Based on LIM. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2006)
Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai
Quasi-One-Step Gauss-Jacobi Method for Large-Scale Interconnect Analysis via RLCG-MNA Formulation. ISQED (2006)
Takayuki Watanabe, Yuichi Tanji, Hidemasa Kubota, Hideki Asai
Parallel-distributed time-domain circuit simulation of power distribution networks with frequency-dependent parameters. ASP-DAC (2006)
Takafumi Yamamoto, Tsutomu Suzuki, Hideki Asai
Concurrent Design of Delta-Sigma Modulator Using Behavioral Modeling and Simulation with the Verilog-A. CICC (2006)
Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai
Large scale RLC circuit analysis using RLCG-MNA formulation. DATE (2006)
Yuichi Tanji, Hideki Asai, Masayoshi Oda, Yoshifumi Nishio, Akio Ushida
Fast timing analysis of plane circuits via two-layer CNN-based modeling. ISCAS (2006)
Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
Modified hybrid reduction technique for the simulation of linear/nonlinear mixed circuits. ISCAS (5) (2005)
Hirokazu Yamagishi, Hiroshi Ninomiya, Hideki Asai
Three dimensional module packing by simulated annealing. Congress on Evolutionary Computation (2005)
Hirofumi Suzuki, Hidemasa Kubota, Takayuki Watanabe, Hideki Asai
Interconnect simulation using FDTD method with variable mesh size technique. ECCTD (2005)
Hidemasa Kubota, Yuichi Tanji, Takayuki Watanabe, Hideki Asai
Generalized method of the time-domain circuit simulation based on LIM with MNA formulation. CICC (2005)
Yuichi Tanji, Masaya Suzuki, Takayuki Watanabe, Hideki Asai
New Criteria of Selective Orthogonal Matrix Least-Squares Method for Macromodeling Multiport Networks Characterized by Sampled Data. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2005)
Takayuki Watanabe, Hideki Asai
Modeling of power distribution networks with signal lines for SPICE simulators. ISCAS (6) (2005)
Yuichi Tanji, Hiroo Sekiya, Hideki Asai
Optimization procedure of class E amplifiers using SPICE. ECCTD (2005)
Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits. DATE (2004)
Yuichi Tanji, Hideki Asai
Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects. DAC (2004)
Takayuki Watanabe, Hideki Asai
Analysis of PCB interconnects using electromagnetic reduction technique. ISCAS (3) (2003)
Shashidhar Tantry, Yasuyuki Hiraku, Takao Oura, Teru Yoneyama, Hideki Asai
A Low Voltage Floating Resistor Circuit Having Both Positive and Negative Resistance Values. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2003)
Yuichi Tanji, Masaya Suzuki, Takayuki Watanabe, Hideki Asai
Behavioral modeling of EM devices by selective orthogonal matrix least-squares method. ASP-DAC (2003)
Takayuki Watanabe, Hideki Asai
A Framework for Macromodeling and Mixed-Mode Simulation of Circuits/Interconnects and Electromagnetic Radiations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2003)
Masahiro Yoshida, Takeshi Kamio, Hideki Asai
Face Image Recognition by 2-Dimensional Discrete Walsh Transform and Multi-Layer Neural Network. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2003)
Takao Oura, Teru Yoneyama, Shashidhar Tantry, Hideki Asai
A threshold voltage independent floating resistor circuit exhibiting both positive and negative resistance values. ISCAS (3) (2002)
Tsutomu Suzuki, Takao Oura, Teru Yoneyama, Hideki Asai
Design and Simulation of 4Q-Multiplier Using Linear and Saturation Regions of MOSFET Complementally. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2002)
Shashidhar Tantry, Takao Oura, Teru Yoneyama, Hideki Asai
A low voltage floating resistor having positive and negative resistance values. APCCAS (1) (2002)
Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
Noise analysis of power/ground planes on PCB by SPICE-like simulator with model order reduction technique. ISCAS (5) (2002)
Kenichi Suzuki, Mitsuhiro Takeda, Atsushi Kamo, Hideki Asai
A Novel Application of Verilog-A to Modeling and Simulation of High-Speed Interconnects in Time/Frequency Transform-Domain. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2002)
I. Hattori, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
Optimal placement of decoupling capacitors on PCB using Poynting vectors obtained by FDTD method. ISCAS (5) (2002)
Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
An Efficient Simulator for Multiport Interconnects with Model Order Reduction Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2002)
Takao Oura, Teru Yoneyama, Shashidhar Tantry, Hideki Asai
A CMOS Floating Resistor Circuit Having Both Positive and Negative Resistance Values. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2002)
Shinsuke Manabe, Hideki Asai
A Neuro-Based Optimization Algorithm for Tiling Problems with Rotation. Neural Process. Lett. 13 (3) (2001)
Shashidhar Tantry, Teru Yoneyama, Hideki Asai
Two floating resistor circuits and their applications to synaptic weights in analog neural networks. ISCAS (1) (2001)
Masaya Suzuki, H. Miyashita, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
High-speed interconnect simulation using MIMO type of adaptive least square method. ISCAS (5) (2001)
Atsushi Kamo, Takayuki Watanabe, Hideki Asai
Simulation for the optimal placement of decoupling capacitors on printed circuit board. ISCAS (3) (2001)
Teru Yoneyama, Hideki Asai, Hiroshi Ninomiya
Design Method of Limit Cycle Generator by Hysteresis Neural Networks. IJCNN (3) (2000)
Masahiro Yoshida, Hideki Asai, Takeshi Kamio
Neuro-Based Human-Face Recognition with 2-Dimensional Discrete Walsh Transform. IJCNN (3) (2000)
Takayuki Watanabe, Hideki Asai
Efficient synthesis technique of time-domain models for interconnects having 3-D structures based on FDTD method. ISCAS (6) (1999)
Teru Yoneyama, Hiroshi Ninomiya, Hideki Asai
Design method of neural networks for limit cycle generator. IJCNN (1999)
Shinsuke Manabe, Hideki Asai
A neuro-based optimization algorithm for tiling problems with rotation. IJCNN (1999)
Atsushi Kamo, Takayuki Watanabe, Hideki Asai
Expanded GMC for transient analysis of transmission line networks. ISCAS (6) (1999)
Hiroshi Sagesaka, Hisashi Irii, Hideki Asai
SPADE : analog/digital mixed signal simulator with analog hardware description language. ICECS (1998)
Atsushi Kamo, Hiroshi Ninomiya, Teru Yoneyama, Hideki Asai
Neural network simulator for spatiotemporal pattern analysis. ICECS (1998)
Takayuki Watanabe, Hideki Asai
Transient analysis for high-speed interconnect networks based on AWE and delay evaluation technique. ICECS (1998)
Hiroyuki Yamamoto, Takeshi Nakayama, Hiroshi Ninomiya, Hideki Asai
Application of neuro-based optimization algorithm to three dimensional cylindric puzzles. ICNN (1997)
Hideki Asai, Takeshi Nakayama, Hiroshi Ninomiya
Tiling algorithm with fitting violation function for analog neural array. ICNN (1996)
Hiroshi Ninomtya, Kunitaka Egawa, Takeshi Kamio, Hideki Asai
Design and implementation of neural network logic circuits with global convergence. ICNN (1996)
Takeshi Kamio, Hiroshi Ninomiya, Hideki Asai
Design and implementation of neuro-based discrete Walsh transform processor. ICNN (1996)
Takayuki Watanabe, Hideki Asai
DESIRE3T+: waveform relaxation-based simulator for coupled lossy transmission lines circuits. ICECS (1996)
Hiroshi Ninomiya, Hideki Asai
Orthogonalized Steepest Descent Method for Solving Nonlinear Equations. ISCAS (1995)
Takeshi Kamio, Hiroshi Ninomiya, Hideki Asai
Convergence of Hopfield Neural Network for Orthogonal Transformation. ISCAS (1995)
Hideki Asai, Katsuaki Onodera, Takeshi Kamio, Hiroshi Ninomiya
A study of Hopfield neural networks with external noises. ICNN (1995)
Hiroshi Ninomiya, Kazumichi Sato, Takeshi Nakayama, Hideki Asai
Neural network approach to traveling salesman problem based on hierarchical city adjacency. ICNN (1995)
Vijaya Gopal Bandi, Hideki Asai
Transient Simulation of Coupled Lossy Interconnects by Window Partitioning Technique. ISCAS (1994)
Masaki Ishida, Koichi Hayashi, Masakatsu Nishigaki, Hideki Asai
Iterated Timing Analysis with Dynamic Partitioning Technique for Bipolar Transistor Circuits. ISCAS (1994)
Takeshi Senoo, Hiroaki Makino, Hideki Asai
Relaxation-Based Steady-State Analysis of Single- and Multi-Conductor Transmission Lines in Frequency Domain. ISCAS (1994)
Masakatsu Nishigaki, Nobuyuki Tanaka, Hideki Asai
Mixed Mode Circuit Simulator SPLIT2.1 using Dynamic Network Separation and Selective Trace. ISCAS (1994)
Hideki Asai, Mitsuo Asai, Mamoru Tanaka
Special parallel processor for lu decomposition of a large-scale sparse matrix. Systems and Computers in Japan 18 (6) (1987)
Hideki Asai, Shinsaku Mori
Network analysis by hierarchical tearing method. Systems and Computers in Japan 16 (6) (1985)